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这是关于如何使用Design Compiler_FPGA Design Flow　软件的说明书。

这是关于如何使用Design Compiler_FPGA Design Flow　软件的说明书。
2016-07-11 10:41:01 下载 43 查看 1,124
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ENVI IDL二次开发中文培训教程 ENVI IDL二次开发中文培训教程

ENVI IDL二次开发中文培训教程 ENVI IDL二次开发中文培训教程
2013-12-31 14:39:01 下载 23 查看 1,116
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该教程是ejb3.0+myeclipse+jboos下开发 ejb的经典教程

该教程是ejb3.0+myeclipse+jboos下开发 ejb的经典教程，希望你能阅读
2016-01-13 00:46:02 下载 130 查看 1,052
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The_Design_Warrior_Guide_To_FPGA.rar

一位老工程师写的关于FPGA方面的书，把多年从事FPGA设计的经验写入书中，读完受益颇多
2013-06-03 13:10:01 下载 172 查看 1,053
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Embedded_Controller_Hardware_Design.pdf

外文书籍，关于嵌入式控制器的硬件设计方面知识，给需要的朋友提供一个参考
2013-04-24 16:38:27 下载 113 查看 1,026
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CMOS Logic Circuit Design (英).pdf

资料->【E】光盘论文->【E5】英文书籍->CMOS Logic Circuit Design (英).pdf
2013-05-22 00:40:01 下载 56 查看 1,100
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SystemVerilog for Design

These extensions address two major aspects of HDL-based design. First, modeling ver
2013-07-14 16:00:01 下载 100 查看 1,108
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Design and Analysis of Analog Filters (英).pdf

资料->【E】光盘论文->【E5】英文书籍->Design and Analysis of Analog Filters (英).pdf
2013-04-24 16:38:50 下载 169 查看 1,149
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Digital Down Converter Design based on FPGA

Digital Down Converter Design based on FPGA.
2013-08-13 12:30:01 下载 165 查看 1,189
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protel99se pcb design

protel99se pcb design
2013-09-11 06:00:02 下载 75 查看 1,080
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Verilog Coding Style for Efficient Digital Design

 

In this paper, we discuss efficient coding and design styles using verilog.
2013-11-22 08:08:02 下载 168 查看 1,232
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High-Speed Digital System Design

Introduce High-Speed Digital System Design.
2013-10-20 02:52:01 下载 191 查看 1,153
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Design Safe Verilog State Machine（Synplicity）

 

One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sour
2013-10-23 20:44:01 下载 141 查看 1,186
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Rf And Microwave Power Amplifier Design（2005）

this book is to present all the relevant informationrequired for RF and micro-wave power amplifier design
2013-12-22 05:20:09 下载 69 查看 1,219
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Verilog Coding Style for Efficient Digital Design

 

In this paper, we discuss efficient coding and design styles using verilog.
2013-11-23 02:48:01 下载 54 查看 1,059
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Design Safe Verilog State Machine（Synplicity）

 

One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sour
2013-10-20 14:40:01 下载 20 查看 1,253
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Verilog Coding Style for Efficient Digital Design

Verilog Coding Style for Efficient Digital Design
2015-01-21 00:47:02 下载 91 查看 1,126
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kangyl_Pci_design_guide_30

kangyl_Pci_design_guide_30
2014-01-08 23:18:02 下载 84 查看 1,020
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Simulation and Synthesis Techniques for Asynchronous FIFO Design

Simulation and Synthesis Techniques for Asynchronous FIFO Design
2013-12-10 01:19:02 下载 27 查看 1,378
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James Armstrong VHDL Design , source code

James Armstrong VHDL Design , source code
2015-04-10 20:18:02 下载 199 查看 1,058
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