📄 usb_int.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 938] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\usb_int.o --depend=.\Obj\usb_int.d --device=DARMSTM --apcs=interwork -O3 -I.\Code\FATSystem\INC -I.\Code\Library\INC -I.\Code\SDCard\INC -I.\Code\Speaker\INC -I.\Code\System\INC -I.\Code\USBMassStorage\INC -I.\Code\User\INC -I.\Code\VS1003\INC -ID:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\Obj\usb_int.crf Code\USBMassStorage\SRC\usb_int.c]
THUMB
AREA ||i.CTR_LP||, CODE, READONLY, ALIGN=2
CTR_LP PROC
;;;41 void CTR_LP(void)
;;;42 {
000000 e92d5ff0 PUSH {r4-r12,lr}
000004 f64b788f MOV r8,#0xbf8f
000008 4f5d LDR r7,|L1.384|
00000a f640768f MOV r6,#0xf8f
00000e f6487a0f MOV r10,#0x8f0f
000012 4d5c LDR r5,|L1.388|
000014 f8dfb170 LDR r11,|L1.392|
;;;43 u32 wEPVal;
;;;44 /* stay in loop while pending ints */
;;;45 while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
000018 e0a9 B |L1.366|
;;;46 {
;;;47 _SetISTR((u16)CLR_CTR); /* clear CTR flag */
00001a bf00 NOP
|L1.28|
00001c f64770ff MOV r0,#0x7fff
000020 f8c50c44 STR r0,[r5,#0xc44]
;;;48 /* extract highest priority endpoint number */
;;;49 EPindex = (u8)(wIstr & ISTR_EP_ID);
000024 f8bb0000 LDRH r0,[r11,#0] ; wIstr
000028 f8df9160 LDR r9,|L1.396|
00002c f000000f AND r0,r0,#0xf
000030 f8890000 STRB r0,[r9,#0] ; EPindex
;;;50 if (EPindex == 0)
000034 b2c0 UXTB r0,r0
000036 2800 CMP r0,#0
000038 d173 BNE |L1.290|
00003a f5056540 ADD r5,r5,#0xc00
;;;51 {
;;;52 /* Decode and service control endpoint interrupt */
;;;53 /* calling related service routine */
;;;54 /* (Setup0_Process, In0_Process, Out0_Process) */
;;;55
;;;56 /* save RX & TX status */
;;;57 /* and set both to NAK */
;;;58 SaveRState = _GetEPRxStatus(ENDP0);
00003e 6828 LDR r0,[r5,#0]
000040 f3c03001 UBFX r0,r0,#12,#2
000044 0300 LSLS r0,r0,#12
000046 8038 STRH r0,[r7,#0] ; SaveRState
;;;59 SaveTState = _GetEPTxStatus(ENDP0);
000048 6828 LDR r0,[r5,#0]
00004a f3c01001 UBFX r0,r0,#4,#2
00004e 0100 LSLS r0,r0,#4
000050 8078 STRH r0,[r7,#2] ; SaveTState
;;;60 _SetEPRxStatus(ENDP0, EP_RX_NAK);
000052 6828 LDR r0,[r5,#0]
000054 b280 UXTH r0,r0
000056 ea000008 AND r0,r0,r8
00005a f4805000 EOR r0,r0,#0x2000
00005e 6028 STR r0,[r5,#0]
;;;61 _SetEPTxStatus(ENDP0, EP_TX_NAK);
000060 6828 LDR r0,[r5,#0]
000062 f64879bf MOV r9,#0x8fbf
000066 b280 UXTH r0,r0
000068 ea000009 AND r0,r0,r9
00006c f0800020 EOR r0,r0,#0x20
000070 6028 STR r0,[r5,#0]
;;;62
;;;63
;;;64 /* DIR bit = origin of the interrupt */
;;;65
;;;66 if ((wIstr & ISTR_DIR) == 0)
000072 f8bb0000 LDRH r0,[r11,#0] ; wIstr
000076 f5a56540 SUB r5,r5,#0xc00 ;61
00007a 06c0 LSLS r0,r0,#27
;;;67 {
;;;68 /* DIR = 0 */
;;;69
;;;70 /* DIR = 0 => IN int */
;;;71 /* DIR = 0 implies that (EP_CTR_TX = 1) always */
;;;72
;;;73
;;;74 _ClearEP_CTR_TX(ENDP0);
00007c f8d50c00 LDR r0,[r5,#0xc00]
000080 d40c BMI |L1.156|
000082 b280 UXTH r0,r0
000084 ea00000a AND r0,r0,r10
000088 f8c50c00 STR r0,[r5,#0xc00]
;;;75 In0_Process();
00008c f7fffffe BL In0_Process
;;;76
;;;77 /* check if SETUP arrived during IN processing */
;;;78 wEPVal = _GetENDPOINT(ENDP0);
000090 f8d50c00 LDR r0,[r5,#0xc00]
;;;79 if ((wEPVal & (EP_CTR_RX | EP_SETUP)) != 0)
000094 f4104f08 TST r0,#0x8800
000098 d021 BEQ |L1.222|
00009a e00d B |L1.184|
|L1.156|
;;;80 {
;;;81 _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
;;;82 Setup0_Process();
;;;83 }
;;;84
;;;85 }
;;;86
;;;87 else
;;;88 {
;;;89 /* DIR = 1 */
;;;90
;;;91 /* DIR = 1 & CTR_RX => SETUP or OUT int */
;;;92 /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
;;;93
;;;94 wEPVal = _GetENDPOINT(ENDP0);
00009c b284 UXTH r4,r0
;;;95 if ((wEPVal & EP_CTR_TX) != 0)
00009e 0620 LSLS r0,r4,#24
0000a0 d508 BPL |L1.180|
;;;96 {
;;;97 _ClearEP_CTR_TX(ENDP0);
0000a2 f8d50c00 LDR r0,[r5,#0xc00]
0000a6 b280 UXTH r0,r0
0000a8 ea00000a AND r0,r0,r10
0000ac f8c50c00 STR r0,[r5,#0xc00]
;;;98 In0_Process();
0000b0 f7fffffe BL In0_Process
|L1.180|
;;;99 }
;;;100 if ((wEPVal &EP_SETUP) != 0)
0000b4 0520 LSLS r0,r4,#20
0000b6 d508 BPL |L1.202|
|L1.184|
;;;101 {
;;;102 _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
0000b8 f8d50c00 LDR r0,[r5,#0xc00]
0000bc b280 UXTH r0,r0
0000be 4030 ANDS r0,r0,r6
0000c0 f8c50c00 STR r0,[r5,#0xc00]
;;;103 Setup0_Process();
0000c4 f7fffffe BL Setup0_Process
0000c8 e009 B |L1.222|
|L1.202|
;;;104 }
;;;105
;;;106 else if ((wEPVal & EP_CTR_RX) != 0)
0000ca 0420 LSLS r0,r4,#16
0000cc d507 BPL |L1.222|
;;;107 {
;;;108 _ClearEP_CTR_RX(ENDP0);
0000ce f8d50c00 LDR r0,[r5,#0xc00]
0000d2 b280 UXTH r0,r0
0000d4 4030 ANDS r0,r0,r6
0000d6 f8c50c00 STR r0,[r5,#0xc00]
;;;109 Out0_Process();
0000da f7fffffe BL Out0_Process
|L1.222|
;;;110 }
;;;111
;;;112 }
;;;113
;;;114 /* before terminate set Tx & Rx status */
;;;115 _SetEPRxStatus(ENDP0, SaveRState);
0000de f8d50c00 LDR r0,[r5,#0xc00]
0000e2 8839 LDRH r1,[r7,#0] ; SaveRState
0000e4 b280 UXTH r0,r0
0000e6 ea000008 AND r0,r0,r8
0000ea 04ca LSLS r2,r1,#19
0000ec d501 BPL |L1.242|
0000ee f4805080 EOR r0,r0,#0x1000
|L1.242|
0000f2 0489 LSLS r1,r1,#18
0000f4 d501 BPL |L1.250|
0000f6 f4805000 EOR r0,r0,#0x2000
|L1.250|
0000fa f8c50c00 STR r0,[r5,#0xc00]
;;;116 _SetEPTxStatus(ENDP0, SaveTState);
0000fe f8d50c00 LDR r0,[r5,#0xc00]
000102 8879 LDRH r1,[r7,#2] ; SaveTState
000104 b280 UXTH r0,r0
000106 ea000009 AND r0,r0,r9
00010a 06ca LSLS r2,r1,#27
00010c d501 BPL |L1.274|
00010e f0800010 EOR r0,r0,#0x10
|L1.274|
000112 0689 LSLS r1,r1,#26
000114 d501 BPL |L1.282|
000116 f0800020 EOR r0,r0,#0x20
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