dsp281x_adc.c

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//###########################################################################
//
// FILE:	DSP281x_Adc.c
//
// TITLE:	DSP281x ADC Initialization & Support Functions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha)
//      |             |      | ADC_usDELAY changed from 5000L to 8000L
//###########################################################################

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

#define ADC_usDELAY  8000L
#define ADC_usDELAY2 20L

//---------------------------------------------------------------------------
// InitAdc: 
//---------------------------------------------------------------------------
// This function initializes ADC to a known state.
//
void InitAdc(void)
{
	extern void DSP28x_usDelay(Uint32 Count);
	
    // To powerup the ADC the ADCENCLK bit should be set first to enable
    // clocks, followed by powering up the bandgap and reference circuitry.
    // After a 5ms delay the rest of the ADC can be powered up. After ADC
    // powerup, another 20us delay is required before performing the first
    // ADC conversion. Please note that for the delay function below to
    // operate correctly the CPU_CLOCK_SPEED define statement in the
    // DSP28_Examples.h file must contain the correct CPU clock period in
    // nanoseconds. For example:

//	AdcRegs.ADCTRL1.bit.RESET = 1;			// Reset the ADC module
//	asm(" RPT #10 || NOP");					// Must wait 12-cycles (worst-case) for ADC reset to take effect
	AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;	// Power up bandgap/reference circuitry
	DELAY_US(ADC_usDELAY);                  // Delay before powering up rest of ADC
	AdcRegs.ADCTRL3.bit.ADCPWDN = 1;		// Power up rest of ADC
	DELAY_US(ADC_usDELAY2);                 // Delay after powering up ADC	
	AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x6;		// ADCCLK=HSPCLK/(2*ADCCLKPS)=18.75MHz
/*** Configure the other ADC register ***/
	AdcRegs.ADCMAXCONV.all = 0x000F;
/*
 bit 15-7      0's:    reserved
 bit 6-4       000:    MAX_CONV2 value
 bit 3-0       0000:   MAX_CONV1 value (0 means 1 conversion)
*/
	AdcRegs.ADCCHSELSEQ1.bit.CONV00=7;
	AdcRegs.ADCCHSELSEQ1.bit.CONV01=6;
	AdcRegs.ADCCHSELSEQ1.bit.CONV02=5;
	AdcRegs.ADCCHSELSEQ1.bit.CONV03=4;
	
	AdcRegs.ADCCHSELSEQ2.bit.CONV04=3;
	AdcRegs.ADCCHSELSEQ2.bit.CONV05=2;
	AdcRegs.ADCCHSELSEQ2.bit.CONV06=1;
	AdcRegs.ADCCHSELSEQ2.bit.CONV07=0;
	
	AdcRegs.ADCCHSELSEQ3.bit.CONV08=8;
	AdcRegs.ADCCHSELSEQ3.bit.CONV09=9;
	AdcRegs.ADCCHSELSEQ3.bit.CONV10=10;
	AdcRegs.ADCCHSELSEQ3.bit.CONV11=11;
	
	AdcRegs.ADCCHSELSEQ4.bit.CONV12=12;
	AdcRegs.ADCCHSELSEQ4.bit.CONV13=13;
	AdcRegs.ADCCHSELSEQ4.bit.CONV14=14;
	AdcRegs.ADCCHSELSEQ4.bit.CONV15=15;
	
	AdcRegs.ADCTRL1.all = 0x2f50;
/*
 bit 15        0:      reserved
 bit 14        0:      RESET, 0=no action, 1=reset ADC
 bit 13-12     10:     SUSMOD, 10=stop after current conversion on emulator suspend
 bit 11-8      1111:   ACQ_PS (Acquisition), 1111 = 8 x ADCCLK
 bit 7         0:      CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
 bit 6         0:      CONT_RUN, 0=start/stop mode, 1=continuous run
 bit 5         0:      SEQ_OVRD, Sequencer override
 bit 4         0:      SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
 bit 3-0       0000:   reserved
*/	
	AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
	AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;	
	
/*
 bit 15        0:      EVB_SOC_SEQ, 0=no action
 bit 14        0:      RST_SEQ1, 0=no action
 bit 13        0:      SOC_SEQ1, 0=clear any pending SOCs
 bit 12        0:      reserved
 bit 11        0:      INT_ENA_SEQ1, 0=disable interrupt
 bit 10        0:      INT_MOD_SEQ1, 0=int on every SEQ1 conv
 bit 9         0:      reserved
 bit 8         0:      EVA_SOC_SEQ1, 0=SEQ1 can't start from EVA
 bit 7         0:      EXT_SOC_SEQ1, 0=SEQ1 can't start from ADCSOC pin
 bit 6         0:      RST_SEQ2, 0=no action
 bit 5         0:      SOC_SEQ2, no effect in cascaded mode
 bit 4         0:      reserved
 bit 3         0:      INT_ENA_SEQ2, 0=int disabled
 bit 2         0:      INT_MOD_SEQ2, 0=int on every other SEQ2 conv
 bit 1         0:      reserved
 bit 0         0:      EVB_SOC_SEQ2, 0=SEQ2 can't started by EVB
*/
}	

//===========================================================================
// No more.
//===========================================================================