cpld_qq2812.rpt

F2812实现电机控制源程序.rar

118  -> - - * - - - - - - - - - - | - - - * - - - - - * - - - - - - | <-- EXINT3
140  -> - * - - - - - - - - - - - | - - - * - - - - - * - - - - - - | <-- EXINT4
80   -> - - - - - - - - - - - * * | - - - - - - - - - * - - - - - - | <-- FIFO_FULL
81   -> - - - - - - - - * - - - - | - - - - - - - - - * - - - - - - | <-- FIFO_PROG
108  -> - - - - - - - - - * - - - | - - - - - - - * - * - - - - - - | <-- IN2
98   -> - - - - - - - - - * - - - | - - - - - - - * - * - - - - - - | <-- IN10
7    -> - - - - - - - - - - * - * | - * - - - - - - - * - - - - - - | <-- Key1
8    -> - - - - - - - * * - - - - | - * - - - - - - - * - - - - - - | <-- Key2
75   -> - - - - - - - - - - * - - | - - - - - - - - - * - - - * - - | <-- PA1
70   -> * - - - - - - - - - - - - | - - * * * * * * * * * * - - - * | <-- WR
LC245-> - - - - - - - - - - * * * | - - - - - - - - - * - - - * - * | <-- DSP_Data1
LC115-> - - - - - - - * * * - - - | - - - - - - - * - * - - - - - - | <-- DSP_Data2
LC243-> - - - - - - * - - - - - - | - - - - - - - - - * - - * - - - | <-- DSP_Data3
LC59 -> - * * * * * - - - - - - - | - - - - - - - - - * - - - - - - | <-- INT1
LC164-> - - - - - - - - - - - - * | - - - - - - - - - * * - - - - - | <-- :242


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'K':

                                       Logic cells placed in LAB 'K'
        +----------------------------- LC171 SICLK
        | +--------------------------- LC173 SIDIN
        | | +------------------------- LC165 TXB1
        | | | +----------------------- LC164 :242
        | | | | +--------------------- LC166 :246
        | | | | | +------------------- LC172 DSP_Data_reg7~1
        | | | | | | +----------------- LC169 DSP_Data_reg7~2
        | | | | | | | +--------------- LC176 DSP_Data_reg6~1
        | | | | | | | | +------------- LC162 DSP_Data_reg6~2
        | | | | | | | | | +----------- LC168 DSP_Data_reg5~1
        | | | | | | | | | | +--------- LC161 DSP_Data_reg5~2
        | | | | | | | | | | | +------- LC170 DSP_Data_reg0~1
        | | | | | | | | | | | | +----- LC163 DSP_Data_reg0~3
        | | | | | | | | | | | | | +--- LC167 DSP_Data_reg0~4
        | | | | | | | | | | | | | | +- LC175 LED_reg_temp2
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'K'
LC      | | | | | | | | | | | | | | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'K':
LC171-> * - - - - - - - - - - - - - - | - - - - - - - - - - * - - - - - | <-- SICLK
LC173-> - * - - - - - - - - - - - - - | - - - - - - - - - - * - - - - - | <-- SIDIN
LC164-> - - - * - - - - - - - - - - - | - - - - - - - - - * * - - - - - | <-- :242
LC166-> - - - - * - - - - - - - - * - | - - - - - - - - - - * - - - - - | <-- :246
LC175-> - - - - - - - - - - - - - - * | - * - - - - - - - - * - - - - - | <-- LED_reg_temp2

Pin
65   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- CS1
44   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42   -> * * - - - * * * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
68   -> - * - - - - - - - - - - - - - | - - * - - * - - * - * - - - - - | <-- DSP_Data1
54   -> * - - - - - - - - - - - - - * | - - * - * - * - - - * - - - - - | <-- DSP_Data2
79   -> - - - - - - - - - - - - * * - | - - - - - - - - - - * - - - - - | <-- FIFO_EMPTY
93   -> - - - - - - - - - - * - - - - | - - - - - - - - - - * - - - - - | <-- IN13
92   -> - - - - - - - - * - - - - - - | - - - - - - - - - - * - - - - - | <-- IN14
91   -> - - - - - - * - - - - - - - - | - - - - - - - - - - * - - - - - | <-- IN15
141  -> - - - - - - - - - - - * - * - | * - - - - - - - - - * - - - - - | <-- Key0
2    -> - - - - - - - - - * * - - - - | - - - - - * - - - - * - - - - - | <-- Key5
1    -> - - - - - - - * * - - - - - - | - - - - - * - - - - * - - - - - | <-- Key6
143  -> - - - - - * * - - - - - - - - | - - - - - * - - - - * - - - - - | <-- Key7
111  -> - - - * * - - - - - - - - - - | - - - * - - - - - - * - - - - - | <-- NMI1
112  -> - - - * * - - - - - - - - - - | - - - * - - - - - - * - - - - - | <-- NMI2
78   -> - - - - - - - - - - - * - - - | - - - - - - - - - - * - - - * - | <-- PA0
86   -> - - * - - - - - - - - - - - - | - - - - - - - - - - * - - - - - | <-- TXB
70   -> * * - - - - - - - - - - - - * | - - * * * * * * * * * * - - - * | <-- WR
LC246-> - - - - - - - - - - - * * * - | - - - - - - - - - - * - - - * * | <-- DSP_Data0
LC241-> - - - - - - - - - * * - - - - | - - - - - - - - - - * - - - - * | <-- DSP_Data5
LC185-> - - - - - - - * * - - - - - - | - - - - - - - - - - * * - - - - | <-- DSP_Data6
LC117-> - - - - - * * - - - - - - - - | - - - - - - - * - - * - - - - - | <-- DSP_Data7
LC56 -> - - - * * - - - - - - - - - - | - - - - - - - - - - * - - - - - | <-- NMI


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'L':

                 Logic cells placed in LAB 'L'
        +------- LC184 DSP_Data4
        | +----- LC185 DSP_Data6
        | | +--- LC179 SLRD
        | | | +- LC181 SLWR
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'L'
LC      | | | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'L':
LC185-> - * - - | - - - - - - - - - - * * - - - - | <-- DSP_Data6

Pin
65   -> - * - - | - - * * * * * * * * * * * * * * | <-- CS1
44   -> - * - - | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45   -> - * - - | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43   -> - * - - | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46   -> - * - - | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41   -> - * - - | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42   -> - * - - | - - * * * * * * * * * * * * * * | <-- DSP_Add5
102  -> - * - - | - - - - - - - - - - - * - - - - | <-- IN6
63   -> * * * - | - - - - - - - * - - - * - - * * | <-- RD
70   -> - - - * | - - * * * * * * * * * * - - - * | <-- WR
LC253-> - - * * | - - - - - - - - - - - * - - * - | <-- SLCS
LC87 -> * - - - | - - - - - - - - - - - * - - - - | <-- ~327~2
LC176-> - * - - | - - - - - - - - - - - * - - - - | <-- DSP_Data_reg6~1
LC162-> - * - - | - - - - - - - - - - - * - - - - | <-- DSP_Data_reg6~2
LC94 -> * - - - | - - - - - - - - - - - * - - - - | <-- DSP_Data_reg4~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'M':

           Logic cells placed in LAB 'M'
        +- LC207 DSP_Data_reg3~1
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'M'
LC      | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'M':

Pin
65   -> * | - - * * * * * * * * * * * * * * | <-- CS1
44   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
107  -> * | - - - - - - - - - - - - * - - - | <-- IN3
97   -> * | - - - - - - - - - - - - * - - - | <-- IN11
6    -> * | - - - - - * - - - - - - * - - - | <-- Key3
LC243-> * | - - - - - - - - - * - - * - - - | <-- DSP_Data3
LC154-> * | - - - - - - - - - * - - * - - - | <-- :213


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'N':

           Logic cells placed in LAB 'N'
        +- LC218 DSP_Data_reg1~2
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'N'
LC      | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'N':

Pin
65   -> * | - - * * * * * * * * * * * * * * | <-- CS1
44   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42   -> * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
99   -> * | - - - - - - - - - - - - - * - * | <-- IN9
75   -> * | - - - - - - - - - * - - - * - - | <-- PA1
LC245-> * | - - - - - - - - - * - - - * - * | <-- DSP_Data1
LC152-> * | - - - - - - - - - * - - - * - * | <-- :215


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'O':

             Logic cells placed in LAB 'O'
        +--- LC227 SLOE
        | +- LC240 DSP_Data_reg0~2
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'O'
LC      | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'O':

Pin
65   -> - * | - - * * * * * * * * * * * * * * | <-- CS1
44   -> - * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45   -> - * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43   -> - * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46   -> - * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41   -> - * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42   -> - * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
100  -> - * | - - - - - - - - - - - - - - * * | <-- IN8
78   -> - * | - - - - - - - - - - * - - - * - | <-- PA0
63   -> * - | - - - - - - - * - - - * - - * * | <-- RD
LC246-> - * | - - - - - - - - - - * - - - * * | <-- DSP_Data0
LC253-> * - | - - - - - - - - - - - * - - * - | <-- SLCS
LC150-> - * | - - - - - - - - - * - - - - * * | <-- :216


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'P':

                       Logic cells placed in LAB 'P'
        +------------- LC246 DSP_Data0
        | +----------- LC245 DSP_Data1
        |