📄 cpld_qq2812.rpt
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** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 145 J OR2 t 0 0 0 1 2 0 2 :212
- 154 J OR2 t 0 0 0 1 2 0 2 :213
- 155 J OR2 t 0 0 0 1 2 0 2 :214
(92) 152 J OR2 t 0 0 0 1 2 1 2 :215
- 150 J OR2 t 0 0 0 1 2 1 2 :216
- 164 K OR2 t 0 0 0 2 2 0 2 :242
- 166 K OR2 t 0 0 0 2 2 0 2 :246
(97) 160 J OR2 s t ! 0 0 0 6 1 1 0 ~327~1
- 87 F OR2 s t ! 0 0 0 6 1 1 0 ~327~2
- 172 K OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg7~1 (~333~1)
(86) 169 K OR2 s t 1 0 1 9 1 1 0 DSP_Data_reg7~2 (~333~2)
(89) 176 K OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg6~1 (~334~1)
- 162 K OR2 s t 1 0 1 9 1 1 0 DSP_Data_reg6~2 (~334~2)
(84) 168 K OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg5~1 (~335~1)
- 161 K OR2 s t 1 0 1 9 1 1 0 DSP_Data_reg5~2 (~335~2)
- 94 F OR2 s t 2 0 1 10 2 1 0 DSP_Data_reg4~1 (~336~1)
- 207 M OR2 s t 2 0 1 10 2 1 0 DSP_Data_reg3~1 (~337~1)
- 151 J OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg2~1 (~338~1)
(91) 149 J OR2 s t 1 0 1 9 1 1 0 DSP_Data_reg2~2 (~338~2)
- 146 J OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg2~3 (~338~3)
- 159 J OR2 s t 1 0 1 9 1 1 0 DSP_Data_reg1~1 (~339~1)
- 218 N OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg1~2 (~339~2)
(96) 157 J OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg1~3 (~339~3)
- 148 J OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg1~4 (~339~4)
- 170 K OR2 s t 1 0 1 9 1 1 0 DSP_Data_reg0~1 (~340~1)
(81) 240 O OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg0~2 (~340~2)
(82) 163 K OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg0~3 (~340~3)
- 167 K OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg0~4 (~340~4)
- 248 P SOFT s t 0 0 0 4 0 0 0 DSP_Data_reg0~5 (~340~5)
- 82 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp7 (:414)
- 90 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp6 (:415)
- 84 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp5 (:416)
- 92 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp4 (:417)
- 95 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp3 (:418)
- 175 K DFFE t 1 1 0 9 1 1 1 LED_reg_temp2 (:419)
- 86 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp1 (:420)
- 81 F DFFE t 1 1 0 9 1 1 1 LED_reg_temp0 (:421)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC11 LED0
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'A':
Pin
141 -> * | * - - - - - - - - - * - - - - - | <-- Key0
LC81 -> * | * - - - - * - - - - - - - - - - | <-- LED_reg_temp0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC21 LED1
| +- LC19 LED2
| |
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'B':
Pin
7 -> * - | - * - - - - - - - * - - - - - - | <-- Key1
8 -> - * | - * - - - - - - - * - - - - - - | <-- Key2
LC175-> - * | - * - - - - - - - - * - - - - - | <-- LED_reg_temp2
LC86 -> * - | - * - - - * - - - - - - - - - - | <-- LED_reg_temp1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------- LC48 OUT7
| +------------- LC45 OUT8
| | +----------- LC43 OUT9
| | | +--------- LC41 OUT10
| | | | +------- LC40 OUT11
| | | | | +----- LC37 OUT12
| | | | | | +--- LC35 OUT13
| | | | | | | +- LC33 OUT14
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'C'
LC | | | | | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'C':
LC48 -> * - - - - - - - | - - * - - - - - - - - - - - - - | <-- OUT7
LC45 -> - * - - - - - - | - - * - - - - - - - - - - - - - | <-- OUT8
LC43 -> - - * - - - - - | - - * - - - - - - - - - - - - - | <-- OUT9
LC41 -> - - - * - - - - | - - * - - - - - - - - - - - - - | <-- OUT10
LC40 -> - - - - * - - - | - - * - - - - - - - - - - - - - | <-- OUT11
LC37 -> - - - - - * - - | - - * - - - - - - - - - - - - - | <-- OUT12
LC35 -> - - - - - - * - | - - * - - - - - - - - - - - - - | <-- OUT13
LC33 -> - - - - - - - * | - - * - - - - - - - - - - - - - | <-- OUT14
Pin
65 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- CS1
44 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42 -> * * * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
69 -> - * - - - - - - | - - * * - * - * * * - - - - - * | <-- DSP_Data0
68 -> - - * - - - - - | - - * - - * - - * - * - - - - - | <-- DSP_Data1
54 -> - - - * - - - - | - - * - * - * - - - * - - - - - | <-- DSP_Data2
67 -> - - - - * - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data3
60 -> - - - - - * - - | - - * - * * * - - - - - - - - - | <-- DSP_Data4
66 -> - - - - - - * - | - - * - * * * - - - - - - - - - | <-- DSP_Data5
61 -> - - - - - - - * | - - * - * * * - - - - - - - - - | <-- DSP_Data6
53 -> * - - - - - - - | - - * * * * - - - - - - - - - - | <-- DSP_Data7
70 -> * * * * * * * * | - - * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------- LC59 INT1
| +----- LC56 NMI
| | +--- LC64 OUT15
| | | +- LC61 SPI_CS
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'D'
LC | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'D':
LC64 -> - - * - | - - - * - - - - - - - - - - - - | <-- OUT15
LC61 -> - - - * | - - - * - - - - - - - - - - - - | <-- SPI_CS
Pin
65 -> - - * * | - - * * * * * * * * * * * * * * | <-- CS1
44 -> - - * * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45 -> - - * * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43 -> - - * * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46 -> - - * * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41 -> - - * * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42 -> - - * * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
69 -> - - - * | - - * * - * - * * * - - - - - * | <-- DSP_Data0
53 -> - - * - | - - * * * * - - - - - - - - - - | <-- DSP_Data7
113 -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT0
116 -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT1
117 -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT2
118 -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT3
140 -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT4
111 -> - * - - | - - - * - - - - - - * - - - - - | <-- NMI1
112 -> - * - - | - - - * - - - - - - * - - - - - | <-- NMI2
70 -> - - * * | - - * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------- LC69 CANTX_1
| +----------- LC80 LCD_Data2
| | +--------- LC78 LCD_Data3
| | | +------- LC77 LCD_Data4
| | | | +----- LC75 LCD_Data5
| | | | | +--- LC73 LCD_Data6
| | | | | | +- LC72 LCD_Data7
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'E'
LC | | | | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'E':
LC80 -> - * - - - - - | - - - - * - - - - - - - - - - - | <-- LCD_Data2
LC78 -> - - * - - - - | - - - - * - - - - - - - - - - - | <-- LCD_Data3
LC77 -> - - - * - - - | - - - - * - - - - - - - - - - - | <-- LCD_Data4
LC75 -> - - - - * - - | - - - - * - - - - - - - - - - - | <-- LCD_Data5
LC73 -> - - - - - * - | - - - - * - - - - - - - - - - - | <-- LCD_Data6
LC72 -> - - - - - - * | - - - - * - - - - - - - - - - - | <-- LCD_Data7
Pin
49 -> * - - - - - - | - - - - * - - - - - - - - - - - | <-- CANTX
65 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- CS1
44 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add0
45 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add1
43 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add2
46 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add3
41 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add4
42 -> - * * * * * * | - - * * * * * * * * * * * * * * | <-- DSP_Add5
54 -> - * - - - - - | - - * - * - * - - - * - - - - - | <-- DSP_Data2
67 -> - - * - - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data3
60 -> - - - * - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data4
66 -> - - - - * - - | - - * - * * * - - - - - - - - - | <-- DSP_Data5
61 -> - - - - - * - | - - * - * * * - - - - - - - - - | <-- DSP_Data6
53 -> - - - - - - * | - - * * * * - - - - - - - - - - | <-- DSP_Data7
70 -> - * * * * * * | - - * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
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