📄 cpld_qq2812.rpt
字号:
OUT11 | 32 77 | GND
GND | 33 76 | VCCIO
OUT12 | 34 75 | PA1
OUT13 | 35 74 | SLOE
OUT14 | 36 73 | VCCIO
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
O S I N D D D D D D B C C V V G D D S S G V G D D C R G C D D D D W S P
U P N M S S S S S S U A A C C N S S L L N C N S S L D N S S S S S R L A
T I T I P P P P P P Z N N C C D P P R W D C D P P K D 1 P P P P C T
1 _ 1 _ _ _ _ _ _ Z R T I I _ _ D R I _ _ O _ _ _ _ S E
5 C A A A A A A E X X O N D D N D D U D D D D N
S d d d d d d R T a a T a a T a a a a D
d d d d d d t t t t t t t t
4 5 2 0 1 3 a a a a a a a a
7 2 4 6 5 3 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 7/ 7(100%) 0/16( 0%) 2/36( 5%)
B: LC17 - LC32 2/16( 12%) 7/ 7(100%) 0/16( 0%) 4/36( 11%)
C: LC33 - LC48 8/16( 50%) 8/ 8(100%) 2/16( 12%) 24/36( 66%)
D: LC49 - LC64 4/16( 25%) 8/ 8(100%) 2/16( 12%) 19/36( 52%)
E: LC65 - LC80 7/16( 43%) 7/ 7(100%) 1/16( 6%) 21/36( 58%)
F: LC81 - LC96 16/16(100%) 7/ 7(100%) 4/16( 25%) 33/36( 91%)
G: LC97 - LC112 5/16( 31%) 6/ 6(100%) 1/16( 6%) 18/36( 50%)
H: LC113 - LC128 4/16( 25%) 7/ 7(100%) 9/16( 56%) 22/36( 61%)
I: LC129 - LC144 4/16( 25%) 7/ 7(100%) 3/16( 18%) 14/36( 38%)
J: LC145 - LC160 13/16( 81%) 6/ 6(100%) 7/16( 43%) 32/36( 88%)
K: LC161 - LC176 15/16( 93%) 7/ 7(100%) 11/16( 68%) 32/36( 88%)
L: LC177 - LC192 4/16( 25%) 7/ 7(100%) 4/16( 25%) 16/36( 44%)
M: LC193 - LC208 1/16( 6%) 8/ 8(100%) 2/16( 12%) 12/36( 33%)
N: LC209 - LC224 1/16( 6%) 7/ 7(100%) 1/16( 6%) 11/36( 30%)
O: LC225 - LC240 2/16( 12%) 6/ 6(100%) 1/16( 6%) 13/36( 36%)
P: LC241 - LC256 7/16( 43%) 7/ 7(100%) 15/16( 93%) 33/36( 91%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 112/112 (100%)
Total logic cells used: 94/256 ( 36%)
Total shareable expanders used: 41/256 ( 16%)
Total Turbo logic cells used: 94/256 ( 36%)
Total shareable expanders not available (n/a): 22/256 ( 8%)
Average fan-in: 8.18
Total fan-in: 769
Total input pins required: 51
Total output pins required: 49
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 94
Total flipflops required: 48
Total product terms required: 332
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 35
Synthesized logic cells: 23/ 256 ( 8%)
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
139 (16) (A) INPUT 0 0 0 0 0 1 0 CANRX_1
49 (120) (H) INPUT 0 0 0 0 0 1 0 CANTX
62 (187) (L) INPUT 0 0 0 0 0 0 0 CLKOUT
65 (192) (L) INPUT 0 0 0 0 0 39 28 CS1
44 (49) (D) INPUT 0 0 0 0 0 39 29 DSP_Add0
45 (128) (H) INPUT 0 0 0 0 0 39 29 DSP_Add1
43 (51) (D) INPUT 0 0 0 0 0 39 29 DSP_Add2
46 (125) (H) INPUT 0 0 0 0 0 39 29 DSP_Add3
41 (54) (D) INPUT 0 0 0 0 0 39 30 DSP_Add4
42 (53) (D) INPUT 0 0 0 0 0 39 30 DSP_Add5
69 246 P BIDIR 5 0 0 10 6 1 4 DSP_Data0 (:340)
68 245 P BIDIR 5 0 0 10 6 1 4 DSP_Data1 (:339)
54 115 H BIDIR 4 0 0 10 4 1 3 DSP_Data2 (:338)
67 243 P BIDIR 0 0 0 1 2 0 2 DSP_Data3 (:337)
60 184 L BIDIR 0 0 0 1 2 0 2 DSP_Data4 (:336)
66 241 P BIDIR 4 0 1 9 3 1 2 DSP_Data5 (:335)
61 185 L BIDIR 4 0 1 9 3 1 2 DSP_Data6 (:334)
53 117 H BIDIR 4 0 1 9 3 1 2 DSP_Data7 (:333)
113 (208) (M) INPUT 0 0 0 0 0 1 1 EXINT0
116 (131) (I) INPUT 0 0 0 0 0 1 1 EXINT1
117 (133) (I) INPUT 0 0 0 0 0 1 1 EXINT2
118 (136) (I) INPUT 0 0 0 0 0 1 1 EXINT3
140 (14) (A) INPUT 0 0 0 0 0 1 1 EXINT4
79 (235) (O) INPUT 0 0 0 0 0 0 2 FIFO_EMPTY
80 (237) (O) INPUT 0 0 0 0 0 0 2 FIFO_FULL
81 (240) (O) INPUT 0 0 0 0 0 0 1 FIFO_PROG
82 (163) (K) INPUT 0 0 0 0 0 0 0 IFCLK
110 (201) (M) INPUT 0 0 0 0 0 1 0 IN0
109 (200) (M) INPUT 0 0 0 0 0 1 0 IN1
108 (197) (M) INPUT 0 0 0 0 0 1 1 IN2
107 (195) (M) INPUT 0 0 0 0 0 0 1 IN3
106 (193) (M) INPUT 0 0 0 0 0 0 1 IN4
103 (221) (N) INPUT 0 0 0 0 0 1 0 IN5
102 (219) (N) INPUT 0 0 0 0 0 1 0 IN6
101 (217) (N) INPUT 0 0 0 0 0 1 0 IN7
100 (216) (N) INPUT 0 0 0 0 0 1 1 IN8
99 (213) (N) INPUT 0 0 0 0 0 1 1 IN9
98 (211) (N) INPUT 0 0 0 0 0 1 1 IN10
97 (160) (J) INPUT 0 0 0 0 0 0 1 IN11
96 (157) (J) INPUT 0 0 0 0 0 0 1 IN12
93 (153) (J) INPUT 0 0 0 0 0 0 1 IN13
92 (152) (J) INPUT 0 0 0 0 0 0 1 IN14
91 (149) (J) INPUT 0 0 0 0 0 0 1 IN15
141 (13) (A) INPUT 0 0 0 0 0 1 2 Key0
7 (25) (B) INPUT 0 0 0 0 0 1 2 Key1
8 (24) (B) INPUT 0 0 0 0 0 1 2 Key2
6 (27) (B) INPUT 0 0 0 0 0 1 1 Key3
5 (29) (B) INPUT 0 0 0 0 0 1 1 Key4
2 (3) (A) INPUT 0 0 0 0 0 1 2 Key5
1 (5) (A) INPUT 0 0 0 0 0 1 2 Key6
143 (6) (A) INPUT 0 0 0 0 0 1 2 Key7
111 (203) (M) INPUT 0 0 0 0 0 1 2 NMI1
112 (206) (M) INPUT 0 0 0 0 0 1 2 NMI2
78 (233) (O) INPUT 0 0 0 0 0 0 2 PA0
75 (229) (O) INPUT 0 0 0 0 0 0 2 PA1
63 (189) (L) INPUT 0 0 0 0 0 10 1 RD
84 (168) (K) INPUT 0 0 0 0 0 0 0 RXB
86 (169) (K) INPUT 0 0 0 0 0 1 0 TXB
70 (249) (P) INPUT 0 0 0 0 0 33 8 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
90 147 J FF t 1 1 0 9 1 1 0 ACICS (:661)
47 123 H FF t 1 0 0 9 1 1 0 BUZZER (:378)
48 121 H OUTPUT t 0 0 0 1 0 0 0 CANRX
138 69 E OUTPUT t 0 0 0 1 0 0 0 CANTX_1
69 246 P TRI/FF t 5 0 0 10 6 1 4 DSP_Data0 (:340)
68 245 P TRI/FF t 5 0 0 10 6 1 4 DSP_Data1 (:339)
54 115 H TRI/FF t 4 0 0 10 4 1 3 DSP_Data2 (:338)
67 243 P TRI/FF t 0 0 0 1 2 0 2 DSP_Data3 (:337)
60 184 L TRI/FF t 0 0 0 1 2 0 2 DSP_Data4 (:336)
66 241 P TRI/FF t 4 0 1 9 3 1 2 DSP_Data5 (:335)
61 185 L TRI/FF t 4 0 1 9 3 1 2 DSP_Data6 (:334)
53 117 H TRI/FF t 4 0 1 9 3 1 2 DSP_Data7 (:333)
120 139 I FF t 1 0 0 9 1 1 0 E (:466)
39 59 D OUTPUT t 0 0 0 5 0 0 5 INT1
121 141 I FF t 1 1 0 9 1 1 0 LCD_Data0 (:524)
122 144 I FF t 1 1 0 9 1 1 0 LCD_Data1 (:523)
131 80 E FF t 1 1 0 9 1 1 0 LCD_Data2 (:522)
132 78 E FF t 1 1 0 9 1 1 0 LCD_Data3 (:521)
133 77 E FF t 1 1 0 9 1 1 0 LCD_Data4 (:520)
134 75 E FF t 1 1 0 9 1 1 0 LCD_Data5 (:519)
136 73 E FF t 1 1 0 9 1 1 0 LCD_Data6 (:518)
137 72 E FF t 1 1 0 9 1 1 0 LCD_Data7 (:517)
142 11 A OUTPUT t 0 0 0 1 1 0 0 LED0
9 21 B OUTPUT t 0 0 0 1 1 0 0 LED1
10 19 B OUTPUT t 0 0 0 1 1 0 0 LED2
11 96 F OUTPUT t 0 0 0 1 1 0 0 LED3
12 93 F OUTPUT t 0 0 0 1 1 0 0 LED4
14 91 F OUTPUT t 0 0 0 1 1 0 0 LED5
15 89 F OUTPUT t 0 0 0 1 1 0 0 LED6
16 88 F OUTPUT t 0 0 0 1 1 0 0 LED7
40 56 D OUTPUT t ! 0 0 0 2 0 0 2 NMI
18 85 F FF t 1 1 0 9 1 1 0 OUT0 (:776)
19 83 F FF t 1 1 0 9 1 1 0 OUT1 (:775)
21 109 G FF t 1 1 0 9 1 1 0 OUT2 (:774)
22 107 G FF t 1 1 0 9 1 1 0 OUT3 (:773)
23 105 G FF t 1 1 0 9 1 1 0 OUT4 (:772)
25 104 G FF t 1 1 0 9 1 1 0 OUT5 (:771)
27 99 G FF t 1 1 0 9 1 1 0 OUT6 (:770)
28 48 C FF t 1 1 0 9 1 1 0 OUT7 (:769)
29 45 C FF t 1 1 0 9 1 1 0 OUT8 (:768)
30 43 C FF t 1 1 0 9 1 1 0 OUT9 (:767)
31 41 C FF t 1 1 0 9 1 1 0 OUT10 (:766)
32 40 C FF t 1 1 0 9 1 1 0 OUT11 (:765)
34 37 C FF t 1 1 0 9 1 1 0 OUT12 (:764)
35 35 C FF t 1 1 0 9 1 1 0 OUT13 (:763)
36 33 C FF t 1 1 0 9 1 1 0 OUT14 (:762)
37 64 D FF t 1 1 0 9 1 1 0 OUT15 (:761)
72 256 P FF t 1 0 0 9 1 1 0 PATEND (:573)
119 137 I FF t 1 0 0 9 1 1 0 RS (:481)
87 171 K FF t 1 1 0 9 1 1 0 SICLK (:677)
88 173 K FF t 1 1 0 9 1 1 0 SIDIN (:669)
71 253 P OUTPUT t ! 0 0 0 7 0 3 0 SLCS
74 227 O OUTPUT s t ! 0 0 0 1 1 0 0 SLOE
55 179 L OUTPUT t ! 0 0 0 1 1 0 0 SLRD
56 181 L OUTPUT t ! 0 0 0 1 1 0 0 SLWR
38 61 D FF t 1 0 0 9 1 1 0 SPI_CS (:646)
83 165 K OUTPUT t 0 0 0 1 0 0 0 TXB1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\work\2812v20\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
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