📄 kernel.h
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/****************************************Copyright (c)****************************
** 贵 州 航 天 3405 厂
** 设计研究所
** 电路组
**
** http://www.ht3405.com
**
**--------------文件信息-----------------------------------------------------------
**文 件 名:KERNEL.h
**创 建 人: 陈兵清
**最后修改日期: 2005年6月30日
**描 述:
**注 意：
**--------------历史版本信息-----------------------------------------------------
** 创建人: 陈兵清
** 日 期: 2005年6月30日
** 描 述: 原始版本。
**
**--------------历史版本信息----------------------------------------------------
** 修改人: 陈兵清
** 日 期: 2005年6月30日
** 描 述:
**--------------历史版本信息---------------------------------------------------*/
#define MAX_BUF 64
// for My Board
#define ISP1581_CS
#define HS_FS_LED
#define ENABLE_1581 IMR|=0x0002;
//#define CHAP9_COMPLIANT 15 //use for chapter 9 and 8 test
//max packet size is 512
//#define USB_ENABLED 3 //to test FIFO must disable DMA_ENABLED and PIO_ENABLED
//USAGE FOR ATA AND ATAPI DEVICE
//#define PIO_ENABLED 1 // to test PIO mode must disable DMA_ENABLED
//#define MDMA_TRANSFER 5 //ATA MDMA Transfer Mode
//#define UDMA_TRANSFER 6 //ATA UDMA Transfer Mode
//#define PIO_TRANSFER 7 //ATA PIO Transfer Mode
//#define DEVICE_ENABLED 8
#define ATAPI_DEVICE 9
//USAGE FOR THE GENERIC DMA MODE
//#define DMA_ENABLED 2 //Select DMA Mode
//#define GDMA_MODE 10 //GDMA Slave Mode
//#define MDMA_MODE 11 //MDMA Master Mode
//#define MPIO_MODE 17 //Manual PIO Mode
//#define PING_PONG 15 //set the descriptor to PID 1582
#define SBUS_RESET 0
#define SSUSPEND 1
#define SPOWER 2
#define SWAKEUP 3
#define SCMD 4
#define SREAD 5
#define SWRITE 6
#define SSTATUS 7
#define Crystal_Freq 12
#define DEVICE_RESET 0x0C
#define ENABLE_INTRQ 0x08
#define DISABLE_INTRQ 0x0A
#define SETUP_DMA_REQUEST 0x7104
#define GET_FIRMWARE_VERSION 0x7204
#define GET_SET_TWAIN_REQUEST 0x7304
#define MASTER_DRIVE 0xA0
#define ATA_MASTER 0
#define ID_ATAPI_DEVICE 0xA1
#define ID_ATA_DEVICE 0xEC
#define ATAPI_SOFTRESET 0x08
#define SET_FEATURE 0xEF
#define INIT_DRIVE 0x91
#define Transfer_Mode 0x03
#define Read 0
#define Write 1
#define GDMA_Read 1
#define GDMA_Write 0
#define GDMA_Start 1
#define GDMA_Stop 0
#define OUT 0
#define IN 1
#define OFF 0
#define ON 1
#define Endpt_Zero 0
#define Endpt_One 1
#define Endpt_Two 2
#define Endpt_Three 3
#define Endpt_Four 4
#define Endpt_Five 5
#define Endpt_Six 6
#define Endpt_Seven 7
#define Control_Type 0
#define Iso_Type 1
#define Bulk_Type 2
#define Int_Type 3
/*
#define Get_Status 0x00
#define Clear_Feature 0x01
#define Set_Feature 0x03
#define Set_Address 0x05
#define Get_Descriptor 0x06
#define Set_Descriptor 0x07
#define Get_Config 0x08
#define Set_Config 0x09
#define Get_Interface 0x0A
#define Set_Interface 0x0B
#define Synch_Frame 0x0C
*/
#define USB_Default 0
#define USB_Addressed 1
#define USB_Configured 2
#define ATAPI_Cmd_Packet_Phase 0x09
#define ATAPI_Message_Phase 0x0B
#define ATAPI_Read_Phase 0x0A
#define ATAPI_Write_Phase 0x08
#define ATAPI_Read_Phase_NODRQ 0x02
#define ATAPI_Write_Phase_NODRQ 0x00
#define ATAPI_Status_Phase 0x03
#define Error_Phase 0xAA
#define No_Data_Phase 0x55
#define Data_Host2Device 0x00
#define Data_Device2Host 0x80
#define TransferData2Host 0x01
#define TransferData2Device 0x02
#define TransferNoData 0x00
#define ATAPI_PACKET_COMMAND 0xA0
#define GDMA_Read_Command 0x00
#define GDMA_Write_Command 0x01
#define UDMA_Read_Command 0x02
#define UDMA_Write_Command 0x03
#define PIO_Read_Command 0x04
#define PIO_Write_Command 0x05
#define MDMA_Read_Command 0x06
#define MDMA_Write_Command 0x07
#define PIO_Write_Complete 0x08
#define PIO_Read_Complete 0x09
#define READ_1F0 0x0A
#define POLL_BUSY 0x0B
#define UPDATE_TASKFILE 0x0C
#define DMA_VALIDATE_BUFFER 0x0E
#define DMA_CLEAR_BUFFER 0x0F
#define DMA_BUFFER_RESTART 0x10
#define DMA_RESET 0x11
#define DMA_FLUSH 0x12
#define GDMA_Test 1
#define UDMA_Test 2
#define MDMA_Test 3
#define PIO_Test 4
#define HIGH_SPEED 0
#define FULL_SPEED 1
#define HIGH_SPEED_LED 0
#define FULL_SPEED_LED 1
#define TEST_MODE 0x0200
#define ENDPOINT_HALT 0
#define DEVICE_REMOTE_WAKEUP 1
#define TEST_J 1
#define TEST_K 2
#define TEST_SE0_NAK 3
#define TEST_PACKET 4
#define TEST_FORCE_ENABLE 5
//***********************************************************************
//* *
//* structure Variable Definition *
//* *
//***********************************************************************/
typedef union KERNEL
{
struct KERNEL_BITS
{
UI TIMER_ONOFF : 1, // F206 timer running state
STATE : 3, //kernel current state
MASTER_ATAPI_DRIVE : 1,
MASTER_ATA_DRIVE : 1,
MASTER_PRESENT : 1,
SLAVE_PRESENT : 1;
UI Manual_PIO : 1,
Auto_PIO : 1,
UDMA_Mode : 1,
MDMA_Mode : 1,
GDMA_Mode : 1,
Timer_Expired : 1,
Bus_Reset : 1;
UI Error_Occur : 2,
Init_Done : 1,
In_Reset_Done : 1,
Out_Reset_Done : 1,
Tx_Done : 1,
Dummy_Byte : 1,
Endpt_Stall : 1;
UI HS_FS_State : 1,
MPIO_Out_Reset_Done : 1,
MPIO_In_Reset_Done : 1,
Register_Test : 1,
Transfer_Error : 1,
Transfer_Start : 1,
ATAPI_DMA_END : 1;
}BITS;
ULI VALUE;
}KERNEL;
typedef struct DRIVE_CONFIG
{
UI General_Config; //word 0
UI PIO_Mode; //word 51
UI MDMA_Mode; //word 63
UI Advanced_PIO; //word 64
UI UDMA_Mode; //word 88
}DRIVE_CONFIG;
/*
typedef struct TIMER
{
UI mSEC_Scale;
UI Hundred_mSEC_Scale;
}TIMER;
*/
typedef struct FEATURE
{
UC SubCommand_Count;
UC SubCommand_Number;
UC SubCommand_Low;
UC SubCommand_High;
}FEATURE;
typedef union DMA_INT_FLAG
{
struct DMA_FLAG_BITS
{
UI CMD_AUTO_COMPLETE : 1;
UI CMD_INTRQ_OK : 1;
UI TASKFILE_READ_COMPLETE : 1;
UI BSY_DRQ_POLL_DONE : 1;
UI START_READ_1F0_RD_FIFO : 1;
UI RD_1F0_FIFO_EMPTY : 1;
UI WR_1F0_FIFO_FULL : 1;
UI WR_1F0_FIFO_EMPTY : 1;
UI DMA_DONE : 1;
UI INTRQ_SEEN : 1;
UI INT_EOT : 1;
UI EXT_EOT : 1;
UI RES1 : 4;
}BITS;
UI VALUE;
}DMA_INT_FLAG;
typedef union DATA_SWAP
{
UC byte[2];
UI word;
}DATA_SWAP;
typedef union ATAPI_BYTECOUNT
{
UC Byte[4];
ULI VALUE;
}ATAPI_BYTECOUNT;
typedef union BYTECOUNT
{
UC Byte[2];
ULI VALUE;
}BYTECOUNT;
/*
typedef union USB_ELEMENT
{
struct USB_ELEMENT_BITS
{
UI SOF_Count : 11,
uSOF_Count : 3;
}BITS;
// UI Value;
}USB_ELEMENT;
*/
typedef union USB_INT_FLAG
{
struct USB_FLAG_BITS
{
UI RESET : 1;
UI SOF : 1;
UI PSOF : 1;
UI SUSP : 1;
UI RESUME : 1;
UI HS_STAT : 1;
UI DMA : 1;
UI RESERVED3 : 1;
UI EP0SETUP : 1;
UI RESERVED2 : 1;
UI EP0RX : 1;
UI EP0TX : 1;
UI EP1RX : 1;
UI EP1TX : 1;
UI EP2RX : 1;
UI EP2TX : 1;
UI EP3RX : 1;
UI EP3TX : 1;
UI EP4RX : 1;
UI EP4TX : 1;
UI EP5RX : 1;
UI EP5TX : 1;
UI EP6RX : 1;
UI EP6TX : 1;
UI EP7RX : 1;
UI EP7TX : 1;
UI RESERVED1 : 6;
}BITS;
UL VALUE;
}USB_INT_FLAG;
typedef struct USB_DEVICE_REQ
{
UC bmRequestType;
UC bRequest;
UI wValue;
UI wIndex;
UI wLength;
}USB_DEVICE_REQ;
typedef struct USB_DEVICE
{
struct USB_DEVICE_BITS
{
UI Remote_Wakeup : 1,
Halt : 1,
Self_Powered : 1,
Endpt_Halt : 1,
Test_Mode : 1,
State : 3;
UI CBI_Detected : 1;
UI DMA_Test_Mode : 8;
UI Alter_Interface : 1,
CBW_Rx : 1,
CBW_Data : 1,
DMA_State : 3,
Big_Endian : 1;
}BITS;
}USB_DEVICE;
typedef struct USBCBW
{
union Signature
{
UC dCBWSignature[4];
ULI VALUE;
}Signature;
UC dCBWTag[4];
union Length
{
UC dCBWDataTransferLength[4];
ULI VALUE;
}Length;
UC dCBWFlags;
UC bCBWLUN;
UC bCDBLength;
UC CBWCDB[0x10];
} USBCBW;
typedef struct USB_CSW
{
union Residue
{
UC dCSWDataResidue[4];
ULI VALUE;
}Residue;
UC bCSWStatus;
}USBCSW;
typedef union FILESIZE
{
struct filesize
{
UC Address[3];
UC FileSize[4];
UC DIR;
}Size;
UDI Value;
}FILESIZE;
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