stm32f10x_rcc.c

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  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
}

/**
  * @brief  Configures the system clock (SYSCLK).
  * @param RCC_SYSCLKSource: specifies the clock source used as system
  *   clock. This parameter can be one of the following values:
  * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
  * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
  * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
  * @retval : None
  */
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
{
  uint32_t tmpreg = 0;
  /* Check the parameters */
  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
  tmpreg = RCC->CFGR;
  /* Clear SW[1:0] bits */
  tmpreg &= CFGR_SW_Mask;
  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
  tmpreg |= RCC_SYSCLKSource;
  /* Store the new value */
  RCC->CFGR = tmpreg;
}

/**
  * @brief  Returns the clock source used as system clock.
  * @param  None
  * @retval : The clock source used as system clock. The returned value can
  *   be one of the following:
  * - 0x00: HSI used as system clock
  * - 0x04: HSE used as system clock
  * - 0x08: PLL used as system clock
  */
uint8_t RCC_GetSYSCLKSource(void)
{
  return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
}

/**
  * @brief  Configures the AHB clock (HCLK).
  * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
  *                    the system clock (SYSCLK).
  *   This parameter can be one of the following values:
  * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
  * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
  * @retval : None
  */
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
{
  uint32_t tmpreg = 0;
  /* Check the parameters */
  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
  tmpreg = RCC->CFGR;
  /* Clear HPRE[3:0] bits */
  tmpreg &= CFGR_HPRE_Reset_Mask;
  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
  tmpreg |= RCC_SYSCLK;
  /* Store the new value */
  RCC->CFGR = tmpreg;
}

/**
  * @brief  Configures the Low Speed APB clock (PCLK1).
  * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
  *                  the AHB clock (HCLK).
  *   This parameter can be one of the following values:
  * @arg RCC_HCLK_Div1: APB1 clock = HCLK
  * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
  * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
  * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
  * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
  * @retval : None
  */
void RCC_PCLK1Config(uint32_t RCC_HCLK)
{
  uint32_t tmpreg = 0;
  /* Check the parameters */
  assert_param(IS_RCC_PCLK(RCC_HCLK));
  tmpreg = RCC->CFGR;
  /* Clear PPRE1[2:0] bits */
  tmpreg &= CFGR_PPRE1_Reset_Mask;
  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
  tmpreg |= RCC_HCLK;
  /* Store the new value */
  RCC->CFGR = tmpreg;
}

/**
  * @brief  Configures the High Speed APB clock (PCLK2).
  * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
  *                  the AHB clock (HCLK).
  *   This parameter can be one of the following values:
  * @arg RCC_HCLK_Div1: APB2 clock = HCLK
  * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
  * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
  * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
  * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
  * @retval : None
  */
void RCC_PCLK2Config(uint32_t RCC_HCLK)
{
  uint32_t tmpreg = 0;
  /* Check the parameters */
  assert_param(IS_RCC_PCLK(RCC_HCLK));
  tmpreg = RCC->CFGR;
  /* Clear PPRE2[2:0] bits */
  tmpreg &= CFGR_PPRE2_Reset_Mask;
  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
  tmpreg |= RCC_HCLK << 3;
  /* Store the new value */
  RCC->CFGR = tmpreg;
}

/**
  * @brief  Enables or disables the specified RCC interrupts.
  * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
  *   This parameter can be any combination of the following values:
  * @arg RCC_IT_LSIRDY: LSI ready interrupt
  * @arg RCC_IT_LSERDY: LSE ready interrupt
  * @arg RCC_IT_HSIRDY: HSI ready interrupt
  * @arg RCC_IT_HSERDY: HSE ready interrupt
  * @arg RCC_IT_PLLRDY: PLL ready interrupt
  * @param NewState: new state of the specified RCC interrupts.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval : None
  */
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_IT(RCC_IT));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  {
    /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
  }
  else
  {
    /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
  }
}

/**
  * @brief  Configures the USB clock (USBCLK).
  * @param RCC_USBCLKSource: specifies the USB clock source. This clock is 
  *                          derived from the PLL output.
  *   This parameter can be one of the following values:
  * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
  *                                     clock source
  * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
  * @retval : None
  */
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
{
  /* Check the parameters */
  assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
  *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
}

/**
  * @brief  Configures the ADC clock (ADCCLK).
  * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
  *                   the APB2 clock (PCLK2).
  *   This parameter can be one of the following values:
  * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
  * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
  * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
  * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
  * @retval : None
  */
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
{
  uint32_t tmpreg = 0;
  /* Check the parameters */
  assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
  tmpreg = RCC->CFGR;
  /* Clear ADCPRE[1:0] bits */
  tmpreg &= CFGR_ADCPRE_Reset_Mask;
  /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
  tmpreg |= RCC_PCLK2;
  /* Store the new value */
  RCC->CFGR = tmpreg;
}

/**
  * @brief  Configures the External Low Speed oscillator (LSE).
  * @param RCC_LSE: specifies the new state of the LSE.
  *   This parameter can be one of the following values:
  * @arg RCC_LSE_OFF: LSE oscillator OFF
  * @arg RCC_LSE_ON: LSE oscillator ON
  * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external
  *   clock
  * @retval : None
  */
void RCC_LSEConfig(uint8_t RCC_LSE)
{
  /* Check the parameters */
  assert_param(IS_RCC_LSE(RCC_LSE));
  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
  /* Reset LSEON bit */
  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  /* Reset LSEBYP bit */
  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
  switch(RCC_LSE)
  {
    case RCC_LSE_ON:
      /* Set LSEON bit */
      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
      break;
      
    case RCC_LSE_Bypass:
      /* Set LSEBYP and LSEON bits */
      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
      break;            
      
    default:
      break;      
  }
}

/**
  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
  *   LSI can not be disabled if the IWDG is running.
  * @param NewState: new state of the LSI.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval : None
  */
void RCC_LSICmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
}

/**
  * @brief  Configures the RTC clock (RTCCLK).
  *   Once the RTC clock is selected it can抰 be changed unless the
  *   Backup domain is reset.
  * @param RCC_RTCCLKSource: specifies the RTC clock source.
  *   This parameter can be one of the following values:
  * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
  *   selected as RTC clock
  * @retval : None
  */
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
{
  /* Check the parameters */
  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
  /* Select the RTC clock source */
  RCC->BDCR |= RCC_RTCCLKSource;
}

/**
  * @brief  Enables or disables the RTC clock.
  *   This function must be used only after the RTC clock was
  *   selected using the RCC_RTCCLKConfig function.
  * @param NewState: new state of the RTC clock.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval : None
  */
void RCC_RTCCLKCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
}

/**
  * @brief  Returns the frequencies of different on chip clocks.
  * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
  *   will hold the clocks frequencies.
  * @retval : None
  */
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & CFGR_SWS_Mask;
  switch (tmp)
  {
    case 0x00:  /* HSI used as system clock */
      RCC_Clocks->SYSCLK_Frequency = HSI_Value;
      break;
    case 0x04:  /* HSE used as system clock */
      RCC_Clocks->SYSCLK_Frequency = HSE_Value;
      break;
    case 0x08:  /* PLL used as system clock */
      /* Get PLL clock source and multiplication factor ----------------------*/
      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
      pllmull = ( pllmull >> 18) + 2;
      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
      if (pllsource == 0x00)
      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
        RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
      }
      else
      {/* HSE selected as PLL clock entry */
        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
        {/* HSE oscillator clock divided by 2 */
          RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
        }
        else
        {
          RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
        }
      }
      break;
    default:
      RCC_Clocks->SYSCLK_Frequency = HSI_Value;
      break;
  }
  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
  /* Get HCLK prescaler */
  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
  tmp = tmp >> 4;
  presc = APBAHBPrescTable[tmp];
  /* HCLK clock frequency */
  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
  /* Get PCLK1 prescaler */
  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
  tmp = tmp >> 8;
  presc = APBAHBPrescTable[tmp];
  /* PCLK1 clock frequency */
  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  /* Get PCLK2 prescaler */
  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;