📄 stm32f10x_map.h
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EXT GPIO_TypeDef *GPIOG;
#endif /*_GPIOG */
#ifdef _ADC1
EXT ADC_TypeDef *ADC1;
#endif /*_ADC1 */
#ifdef _ADC2
EXT ADC_TypeDef *ADC2;
#endif /*_ADC2 */
#ifdef _TIM1
EXT TIM_TypeDef *TIM1;
#endif /*_TIM1 */
#ifdef _SPI1
EXT SPI_TypeDef *SPI1;
#endif /*_SPI1 */
#ifdef _TIM8
EXT TIM_TypeDef *TIM8;
#endif /*_TIM8 */
#ifdef _USART1
EXT USART_TypeDef *USART1;
#endif /*_USART1 */
#ifdef _ADC3
EXT ADC_TypeDef *ADC3;
#endif /*_ADC3 */
#ifdef _SDIO
EXT SDIO_TypeDef *SDIO;
#endif /*_SDIO */
#ifdef _DMA
EXT DMA_TypeDef *DMA1;
EXT DMA_TypeDef *DMA2;
#endif /*_DMA */
#ifdef _DMA1_Channel1
EXT DMA_Channel_TypeDef *DMA1_Channel1;
#endif /*_DMA1_Channel1 */
#ifdef _DMA1_Channel2
EXT DMA_Channel_TypeDef *DMA1_Channel2;
#endif /*_DMA1_Channel2 */
#ifdef _DMA1_Channel3
EXT DMA_Channel_TypeDef *DMA1_Channel3;
#endif /*_DMA1_Channel3 */
#ifdef _DMA1_Channel4
EXT DMA_Channel_TypeDef *DMA1_Channel4;
#endif /*_DMA1_Channel4 */
#ifdef _DMA1_Channel5
EXT DMA_Channel_TypeDef *DMA1_Channel5;
#endif /*_DMA1_Channel5 */
#ifdef _DMA1_Channel6
EXT DMA_Channel_TypeDef *DMA1_Channel6;
#endif /*_DMA1_Channel6 */
#ifdef _DMA1_Channel7
EXT DMA_Channel_TypeDef *DMA1_Channel7;
#endif /*_DMA1_Channel7 */
#ifdef _DMA2_Channel1
EXT DMA_Channel_TypeDef *DMA2_Channel1;
#endif /*_DMA2_Channel1 */
#ifdef _DMA2_Channel2
EXT DMA_Channel_TypeDef *DMA2_Channel2;
#endif /*_DMA2_Channel2 */
#ifdef _DMA2_Channel3
EXT DMA_Channel_TypeDef *DMA2_Channel3;
#endif /*_DMA2_Channel3 */
#ifdef _DMA2_Channel4
EXT DMA_Channel_TypeDef *DMA2_Channel4;
#endif /*_DMA2_Channel4 */
#ifdef _DMA2_Channel5
EXT DMA_Channel_TypeDef *DMA2_Channel5;
#endif /*_DMA2_Channel5 */
#ifdef _RCC
EXT RCC_TypeDef *RCC;
#endif /*_RCC */
#ifdef _CRC
EXT CRC_TypeDef *CRC;
#endif /*_CRC */
#ifdef _FLASH
EXT FLASH_TypeDef *FLASH;
EXT OB_TypeDef *OB;
#endif /*_FLASH */
#ifdef _FSMC
EXT FSMC_Bank1_TypeDef *FSMC_Bank1;
EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E;
EXT FSMC_Bank2_TypeDef *FSMC_Bank2;
EXT FSMC_Bank3_TypeDef *FSMC_Bank3;
EXT FSMC_Bank4_TypeDef *FSMC_Bank4;
#endif /*_FSMC */
#ifdef _DBGMCU
EXT DBGMCU_TypeDef *DBGMCU;
#endif /*_DBGMCU */
#ifdef _SysTick
EXT SysTick_TypeDef *SysTick;
#endif /*_SysTick */
#ifdef _NVIC
EXT NVIC_TypeDef *NVIC;
EXT SCB_TypeDef *SCB;
#endif /*_NVIC */
#endif /* DEBUG */
/* Exported constants --------------------------------------------------------*/
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((u8)0x01) /* RESET bit */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
#define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */
#define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */
#define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */
#define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */
#define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */
#define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
#define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */
#define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */
#define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */
/* PVD level configuration */
#define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */
#define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */
#define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */
#define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */
#define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */
#define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */
#define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */
#define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */
#define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */
#define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */
#define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */
#define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */
/******************************************************************************/
/* */
/* Backup registers */
/* */
/******************************************************************************/
/******************* Bit definition for BKP_DR1 register ********************/
#define BKP_DR1_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR2 register ********************/
#define BKP_DR2_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR3 register ********************/
#define BKP_DR3_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR4 register ********************/
#define BKP_DR4_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR5 register ********************/
#define BKP_DR5_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR6 register ********************/
#define BKP_DR6_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR7 register ********************/
#define BKP_DR7_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR8 register ********************/
#define BKP_DR8_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR9 register ********************/
#define BKP_DR9_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR10 register *******************/
#define BKP_DR10_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR11 register *******************/
#define BKP_DR11_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR12 register *******************/
#define BKP_DR12_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR13 register *******************/
#define BKP_DR13_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR14 register *******************/
#define BKP_DR14_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR15 register *******************/
#define BKP_DR15_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR16 register *******************/
#define BKP_DR16_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR17 register *******************/
#define BKP_DR17_D ((u16)0xFFFF) /* Backup data */
/****************** Bit definition for BKP_DR18 register ********************/
#define BKP_DR18_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR19 register *******************/
#define BKP_DR19_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR20 register *******************/
#define BKP_DR20_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR21 register *******************/
#define BKP_DR21_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR22 register *******************/
#define BKP_DR22_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR23 register *******************/
#define BKP_DR23_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR24 register *******************/
#define BKP_DR24_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR25 register *******************/
#define BKP_DR25_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR26 register *******************/
#define BKP_DR26_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR27 register *******************/
#define BKP_DR27_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR28 register *******************/
#define BKP_DR28_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR29 register *******************/
#define BKP_DR29_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR30 register *******************/
#define BKP_DR30_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR31 register *******************/
#define BKP_DR31_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR32 register *******************/
#define BKP_DR32_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR33 register *******************/
#define BKP_DR33_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR34 register *******************/
#define BKP_DR34_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR35 register *******************/
#define BKP_DR35_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR36 register *******************/
#define BKP_DR36_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR37 register *******************/
#define BKP_DR37_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR38 register *******************/
#define BKP_DR38_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR39 register *******************/
#define BKP_DR39_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR40 register *******************/
#define BKP_DR40_D ((u16)0xFFFF) /* Backup data */
/******************* Bit definition for BKP_DR41 register *******************/
#define BKP_DR41_D ((u16)0xFFFF) /* Backup data */
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