mcf52233.h

基于32位ColdFire构建嵌入式系统书本原程序.rar

#define MCF_GPIO_PDSRL_PDSR17          (0x00020000)
#define MCF_GPIO_PDSRL_PDSR18          (0x00040000)
#define MCF_GPIO_PDSRL_PDSR19          (0x00080000)
#define MCF_GPIO_PDSRL_PDSR20          (0x00100000)
#define MCF_GPIO_PDSRL_PDSR21          (0x00200000)
#define MCF_GPIO_PDSRL_PDSR22          (0x00400000)
#define MCF_GPIO_PDSRL_PDSR23          (0x00800000)
#define MCF_GPIO_PDSRL_PDSR24          (0x01000000)
#define MCF_GPIO_PDSRL_PDSR25          (0x02000000)
#define MCF_GPIO_PDSRL_PDSR26          (0x04000000)
#define MCF_GPIO_PDSRL_PDSR27          (0x08000000)
#define MCF_GPIO_PDSRL_PDSR28          (0x10000000)
#define MCF_GPIO_PDSRL_PDSR29          (0x20000000)
#define MCF_GPIO_PDSRL_PDSR30          (0x40000000)
#define MCF_GPIO_PDSRL_PDSR31          (0x80000000)

/*********************************************************************
*
* FlexCAN Module (CAN)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CAN_CANMCR                   (*(vuint32*)(&__IPSBAR[0x1C0000]))
#define MCF_CAN_CANCTRL                  (*(vuint32*)(&__IPSBAR[0x1C0004]))
#define MCF_CAN_TIMER                    (*(vuint32*)(&__IPSBAR[0x1C0008]))
#define MCF_CAN_RXGMASK                  (*(vuint32*)(&__IPSBAR[0x1C0010]))
#define MCF_CAN_RX14MASK                 (*(vuint32*)(&__IPSBAR[0x1C0014]))
#define MCF_CAN_RX15MASK                 (*(vuint32*)(&__IPSBAR[0x1C0018]))
#define MCF_CAN_ERRCNT                   (*(vuint32*)(&__IPSBAR[0x1C001C]))
#define MCF_CAN_ERRSTAT                  (*(vuint32*)(&__IPSBAR[0x1C0020]))
#define MCF_CAN_IMASK                    (*(vuint32*)(&__IPSBAR[0x1C0028]))
#define MCF_CAN_IFLAG                    (*(vuint32*)(&__IPSBAR[0x1C0030]))
/* Bit definitions and macros for MCF_CAN_CANMCR */
#define MCF_CAN_CANMCR_MAXMB(x)          (((x)&0x0000000F)<<0)
#define MCF_CAN_CANMCR_SUPV              (0x00800000)
#define MCF_CAN_CANMCR_FRZACK            (0x01000000)
#define MCF_CAN_CANMCR_SOFTRST           (0x02000000)
#define MCF_CAN_CANMCR_HALT              (0x10000000)
#define MCF_CAN_CANMCR_FRZ               (0x40000000)
#define MCF_CAN_CANMCR_MDIS              (0x80000000)
/* Bit definitions and macros for MCF_CAN_CANCTRL */
#define MCF_CAN_CANCTRL_PROPSEG(x)       (((x)&0x00000007)<<0)
#define MCF_CAN_CANCTRL_LOM              (0x00000008)
#define MCF_CAN_CANCTRL_LBUF             (0x00000010)
#define MCF_CAN_CANCTRL_TSYNC            (0x00000020)
#define MCF_CAN_CANCTRL_BOFFREC          (0x00000040)
#define MCF_CAN_CANCTRL_SAMP             (0x00000080)
#define MCF_CAN_CANCTRL_LPB              (0x00001000)
#define MCF_CAN_CANCTRL_CLKSRC           (0x00002000)
#define MCF_CAN_CANCTRL_ERRMSK           (0x00004000)
#define MCF_CAN_CANCTRL_BOFFMSK          (0x00008000)
#define MCF_CAN_CANCTRL_PSEG2(x)         (((x)&0x00000007)<<16)
#define MCF_CAN_CANCTRL_PSEG1(x)         (((x)&0x00000007)<<19)
#define MCF_CAN_CANCTRL_RJW(x)           (((x)&0x00000003)<<22)
#define MCF_CAN_CANCTRL_PRESDIV(x)       (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_CAN_TIMER */
#define MCF_CAN_TIMER_TIMER(x)           (((x)&0x0000FFFF)<<0)
/* Bit definitions and macros for MCF_CAN_RXGMASK */
#define MCF_CAN_RXGMASK_MI(x)            (((x)&0x1FFFFFFF)<<0)
/* Bit definitions and macros for MCF_CAN_RX14MASK */
#define MCF_CAN_RX14MASK_MI(x)           (((x)&0x1FFFFFFF)<<0)
/* Bit definitions and macros for MCF_CAN_RX15MASK */
#define MCF_CAN_RX15MASK_MI(x)           (((x)&0x1FFFFFFF)<<0)
/* Bit definitions and macros for MCF_CAN_ERRCNT */
#define MCF_CAN_ERRCNT_TXECTR(x)         (((x)&0x000000FF)<<0)
#define MCF_CAN_ERRCNT_RXECTR(x)         (((x)&0x000000FF)<<8)
/* Bit definitions and macros for MCF_CAN_ERRSTAT */
#define MCF_CAN_ERRSTAT_WAKINT           (0x00000001)
#define MCF_CAN_ERRSTAT_ERRINT           (0x00000002)
#define MCF_CAN_ERRSTAT_BOFFINT          (0x00000004)
#define MCF_CAN_ERRSTAT_FLTCONF(x)       (((x)&0x00000003)<<4)
#define MCF_CAN_ERRSTAT_TXRX             (0x00000040)
#define MCF_CAN_ERRSTAT_IDLE             (0x00000080)
#define MCF_CAN_ERRSTAT_RXWRN            (0x00000100)
#define MCF_CAN_ERRSTAT_TXWRN            (0x00000200)
#define MCF_CAN_ERRSTAT_STFERR           (0x00000400)
#define MCF_CAN_ERRSTAT_FRMERR           (0x00000800)
#define MCF_CAN_ERRSTAT_CRCERR           (0x00001000)
#define MCF_CAN_ERRSTAT_ACKERR           (0x00002000)
#define MCF_CAN_ERRSTAT_BITERR(x)        (((x)&0x00000003)<<14)
#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE   (0x00000000)
#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE  (0x00000010)
#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF   (0x00000020)
/* Bit definitions and macros for MCF_CAN_IMASK */
#define MCF_CAN_IMASK_BUF0M              (0x0001)
#define MCF_CAN_IMASK_BUF1M              (0x0002)
#define MCF_CAN_IMASK_BUF2M              (0x0004)
#define MCF_CAN_IMASK_BUF3M              (0x0008)
#define MCF_CAN_IMASK_BUF4M              (0x0010)
#define MCF_CAN_IMASK_BUF5M              (0x0020)
#define MCF_CAN_IMASK_BUF6M              (0x0040)
#define MCF_CAN_IMASK_BUF7M              (0x0080)
#define MCF_CAN_IMASK_BUF8M              (0x0100)
#define MCF_CAN_IMASK_BUF9M              (0x0200)
#define MCF_CAN_IMASK_BUF10M             (0x0400)
#define MCF_CAN_IMASK_BUF11M             (0x0800)
#define MCF_CAN_IMASK_BUF12M             (0x1000)
#define MCF_CAN_IMASK_BUF13M             (0x2000)
#define MCF_CAN_IMASK_BUF14M             (0x4000)
#define MCF_CAN_IMASK_BUF15M             (0x8000)
/* Bit definitions and macros for MCF_CAN_IFLAG */
#define MCF_CAN_IFLAG_BUF0I              (0x0001)
#define MCF_CAN_IFLAG_BUF1I              (0x0002)
#define MCF_CAN_IFLAG_BUF2I              (0x0004)
#define MCF_CAN_IFLAG_BUF3I              (0x0008)
#define MCF_CAN_IFLAG_BUF4I              (0x0010)
#define MCF_CAN_IFLAG_BUF5I              (0x0020)
#define MCF_CAN_IFLAG_BUF6I              (0x0040)
#define MCF_CAN_IFLAG_BUF7I              (0x0080)
#define MCF_CAN_IFLAG_BUF8I              (0x0100)
#define MCF_CAN_IFLAG_BUF9I              (0x0200)
#define MCF_CAN_IFLAG_BUF10I             (0x0400)
#define MCF_CAN_IFLAG_BUF11I             (0x0800)
#define MCF_CAN_IFLAG_BUF12I             (0x1000)
#define MCF_CAN_IFLAG_BUF13I             (0x2000)
#define MCF_CAN_IFLAG_BUF14I             (0x4000)
#define MCF_CAN_IFLAG_BUF15I             (0x8000)

/*********************************************************************
*
* ColdFire Flash Module (CFM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CFM_CFMMCR           (*(vuint16*)(&__IPSBAR[0x1D0000]))
#define MCF_CFM_CFMCLKD          (*(vuint8 *)(&__IPSBAR[0x1D0002]))
#define MCF_CFM_CFMSEC           (*(vuint32*)(&__IPSBAR[0x1D0008]))
#define MCF_CFM_CFMPROT          (*(vuint32*)(&__IPSBAR[0x1D0010]))
#define MCF_CFM_CFMSACC          (*(vuint32*)(&__IPSBAR[0x1D0014]))
#define MCF_CFM_CFMDACC          (*(vuint32*)(&__IPSBAR[0x1D0018]))
#define MCF_CFM_CFMUSTAT         (*(vuint8 *)(&__IPSBAR[0x1D0020]))
#define MCF_CFM_CFMCMD           (*(vuint8 *)(&__IPSBAR[0x1D0024]))
/* Bit definitions and macros for MCF_CFM_CFMMCR */
#define MCF_CFM_CFMMCR_KEYACC    (0x0020)
#define MCF_CFM_CFMMCR_CCIE      (0x0040)
#define MCF_CFM_CFMMCR_CBEIE     (0x0080)
#define MCF_CFM_CFMMCR_AEIE      (0x0100)
#define MCF_CFM_CFMMCR_PVIE      (0x0200)
#define MCF_CFM_CFMMCR_LOCK      (0x0400)
/* Bit definitions and macros for MCF_CFM_CFMCLKD */
#define MCF_CFM_CFMCLKD_DIV(x)   (((x)&0x3F)<<0)
#define MCF_CFM_CFMCLKD_PRDIV8   (0x40)
#define MCF_CFM_CFMCLKD_DIVLD    (0x80)
/* Bit definitions and macros for MCF_CFM_CFMSEC */
#define MCF_CFM_CFMSEC_SEC(x)    (((x)&0x0000FFFF)<<0)
#define MCF_CFM_CFMSEC_SECSTAT   (0x40000000)
#define MCF_CFM_CFMSEC_KEYEN     (0x80000000)
/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
#define MCF_CFM_CFMUSTAT_BLANK   (0x04)
#define MCF_CFM_CFMUSTAT_ACCERR  (0x10)
#define MCF_CFM_CFMUSTAT_PVIOL   (0x20)
#define MCF_CFM_CFMUSTAT_CCIF    (0x40)
#define MCF_CFM_CFMUSTAT_CBEIF   (0x80)
/* Bit definitions and macros for MCF_CFM_CFMCMD */
#define MCF_CFM_CFMCMD_CMD(x)    (((x)&0x7F)<<0)
#define MCF_CFM_CFMCMD_RDARY1    (0x05)
#define MCF_CFM_CFMCMD_PGM       (0x20)
#define MCF_CFM_CFMCMD_PGERS     (0x40)
#define MCF_CFM_CFMCMD_MASERS    (0x41)
#define MCF_CFM_CFMCMD_PGERSVER  (0x06)

/*********************************************************************
*
* ColdFire Integration Module (CIM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CIM_RCR             (*(vuint8 *)(&__IPSBAR[0x110000]))
#define MCF_CIM_RSR             (*(vuint8 *)(&__IPSBAR[0x110001]))
#define MCF_CIM_CCR             (*(vuint16*)(&__IPSBAR[0x110004]))
#define MCF_CIM_LPCR            (*(vuint8 *)(&__IPSBAR[0x110007]))
#define MCF_CIM_RCON            (*(vuint16*)(&__IPSBAR[0x110008]))
#define MCF_CIM_CIR             (*(vuint16*)(&__IPSBAR[0x11000A]))
/* Bit definitions and macros for MCF_CIM_RCR */
#define MCF_CIM_RCR_LVDE        (0x01)
#define MCF_CIM_RCR_LVDRE       (0x04)
#define MCF_CIM_RCR_LVDIE       (0x08)
#define MCF_CIM_RCR_LVDF        (0x10)
#define MCF_CIM_RCR_FRCRSTOUT   (0x40)
#define MCF_CIM_RCR_SOFTRST     (0x80)
/* Bit definitions and macros for MCF_CIM_RSR */
#define MCF_CIM_RSR_LOL         (0x01)
#define MCF_CIM_RSR_LOC         (0x02)
#define MCF_CIM_RSR_EXT         (0x04)
#define MCF_CIM_RSR_POR         (0x08)
#define MCF_CIM_RSR_WDR         (0x10)
#define MCF_CIM_RSR_SOFT        (0x20)
#define MCF_CIM_RSR_LVD         (0x40)
/* Bit definitions and macros for MCF_CIM_CCR */
#define MCF_CIM_CCR_LOAD        (0x8000)
/* Bit definitions and macros for MCF_CIM_LPCR */
#define MCF_CIM_LPCR_LVDSE      (0x02)
#define MCF_CIM_LPCR_STPMD(x)   (((x)&0x03)<<3)
#define MCF_CIM_LPCR_LPMD(x)    (((x)&0x03)<<6)
#define MCF_CIM_LPCR_LPMD_STOP  (0xC0)
#define MCF_CIM_LPCR_LPMD_WAIT  (0x80)
#define MCF_CIM_LPCR_LPMD_DOZE  (0x40)
#define MCF_CIM_LPCR_LPMD_RUN   (0x00)
/* Bit definitions and macros for MCF_CIM_RCON */
#define MCF_CIM_RCON_RLOAD      (0x0020)

/*********************************************************************
*
* Clock Module (CLOCK)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CLOCK_SYNCR           (*(vuint16*)(&__IPSBAR[0x120000]))
#define MCF_CLOCK_SYNSR           (*(vuint8 *)(&__IPSBAR[0x120002]))
#define MCF_CLOCK_LPCR            (*(vuint8 *)(&__IPSBAR[0x120007]))
#define MCF_CLOCK_CCHR            (*(vuint8 *)(&__IPSBAR[0x120008]))
#define MCF_CLOCK_RTCDR           (*(vuint32*)(&__IPSBAR[0x12000C]))
/* Bit definitions and macros for MCF_CLOCK_SYNCR */
#define MCF_CLOCK_SYNCR_PLLEN     (0x0001)
#define MCF_CLOCK_SYNCR_PLLMODE   (0x0002)
#define MCF_CLOCK_SYNCR_CLKSRC    (0x0004)
#define MCF_CLOCK_SYNCR_FWKUP     (0x0020)
#define MCF_CLOCK_SYNCR_DISCLK    (0x0040)
#define MCF_CLOCK_SYNCR_LOCEN     (0x0080)
#define MCF_CLOCK_SYNCR_RFD(x)    (((x)&0x0007)<<8)
#define MCF_CLOCK_SYNCR_LOCRE     (0x0800)
#define MCF_CLOCK_SYNCR_MFD(x)    (((x)&0x0007)<<12)
#define MCF_CLOCK_SYNCR_LOLRE     (0x8000)
/* Bit definitions and macros for MCF_CLOCK_SYNSR */
#define MCF_CLOCK_SYNSR_LOCS      (0x04)
#define MCF_CLOCK_SYNSR_LOCK      (0x08)
#define MCF_CLOCK_SYNSR_LOCKS     (0x10)
#define MCF_CLOCK_SYNSR_CRYOSC    (0x20)
#define MCF_CLOCK_SYNSR_OCOSC     (0x40)
#define MCF_CLOCK_SYNSR_EXTOSC    (0x80)
/* Bit definitions and macros for MCF_CLOCK_LPCR */
#define MCF_CLOCK_LPCR_LPD(x)     (((x)&0x0F)<<0)
/* Bit definitions and macros for MCF_CLOCK_CCHR */
#define MCF_CLOCK_CCHR_PFD(x)     (((x)&0x07)<<0)
/* Bit definitions and macros for MCF_CLOCK_RTCDR */
#define MCF_CLOCK_RTCDR_RTCDF(x)  (((x)&0xFFFFFFFF)<<0)

/*********************************************************************
*
* DMA Controller Module (DMA)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DMA_DMAREQC                 (*(vuint32*)(&__IPSBAR[0x000014]))
#define MCF_DMA_SAR0                    (*(vuint32*)(&__IPSBAR[0x000100]))
#define MCF_DMA_SAR1                    (*(vuint32*)(&__IPSBAR[0x000110]))
#define MCF_DMA_SAR2                    (*(vuint32*)(&__IPSBAR[0x000120]))
#define MCF_DMA_SAR3                    (*(vuint32*)(&__IPSBAR[0x000130]))
#define MCF_DMA_SAR(x)                  (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)]))
#define MCF_DMA_DAR0                    (*(vuint32*)(&__IPSBAR[0x000104]))
#define MCF_DMA_DAR1                    (*(vuint32*)(&__IPSBAR[0x000114]))
#define MCF_DMA_DAR2                    (*(vuint32*)(&__IPSBAR[0x000124]))
#define MCF_DMA_DAR3                    (*(vuint32*)(&__IPSBAR[0x000134]))
#define MCF_DMA_DAR(x)                  (*(vui