nvram.lst

MSTARXX.rar

                      MCUXFR_40_SSPI_WD0=0xab;
                      MCUXFR_41_SSPI_WD1=0x00;
                      MCUXFR_42_SSPI_WD2=0x00;
                      MCUXFR_43_SSPI_WD3=0x00;
                      MCUXFR_48_SSPI_TRIG=0xc4;
              
                      i=MCUXFR_4C_SSPI_RD3; // PMC Manufacture ID =0x9d
              
                      if (i==0x9d)
                      {
                              // PMC flash
              
                              // 20051207 seven
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xf8;
              
                              // Write Status 0x00
                              MCUXFR_40_SSPI_WD0=0x01;
                              MCUXFR_41_SSPI_WD1=0x00;
                              MCUXFR_48_SSPI_TRIG=0xf9;
              
                              // Write Enable WREN + Sector Erase
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xf8;
                              MCUXFR_40_SSPI_WD0=0xd7; //  Sector Erase 0x00e000
                              MCUXFR_41_SSPI_WD1=(BYTE)(address);
                              MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
                              MCUXFR_43_SSPI_WD3=0x00;
                              MCUXFR_48_SSPI_TRIG=0xfb;
                              Delay1ms(100);
              
                              // WREN + Write Byte
                              for (i=0;i<sizeof(g_VideoSetting);i++)
                              {
                                      MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                                      MCUXFR_48_SSPI_TRIG=0xf8;
                                      MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
                                      MCUXFR_41_SSPI_WD1=(BYTE)(address);
                                      MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
                                      MCUXFR_43_SSPI_WD3=i;
                                      MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
                                      MCUXFR_48_SSPI_TRIG=0xfc;
                                      Delay1ms(5);
                              }
              
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xf8;
              
                              // Write Status 0x0C    // 20051207 seven
C51 COMPILER V8.18   NVRAM                                                                 09/29/2009 23:58:03 PAGE 5   

                              MCUXFR_40_SSPI_WD0=0x01;
                              MCUXFR_41_SSPI_WD1=0x0C;
                              MCUXFR_48_SSPI_TRIG=0xf9;
              
                              //  Write disable       : Reset write enable latch
                              MCUXFR_40_SSPI_WD0=0x04;  // Write disable
                              MCUXFR_48_SSPI_TRIG=0xf8;
                              //sysWriteString("Save Flash Data finish.\x0d\x0a");
              
                      }
                      else if(i==0x05)//20050923
                      {
                              // SAIFUN flash
                              // 20051207 seven
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xf8;
              
                              // Write Status 0x00
                              MCUXFR_40_SSPI_WD0=0x01;
                              MCUXFR_41_SSPI_WD1=0x00;
                              MCUXFR_48_SSPI_TRIG=0xF9;
              
                              // Write Enable WREN + Sector Erase
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xF8;
                              MCUXFR_40_SSPI_WD0=0x81; //  Sector Erase 0x00e000
                              MCUXFR_41_SSPI_WD1=(BYTE)(address);
                              MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
                              MCUXFR_43_SSPI_WD3=0x00;
                              MCUXFR_48_SSPI_TRIG=0xFb;
                              Delay1ms(6);
              
                              // WREN + Write Byte
                              for (i=0;i<sizeof(g_VideoSetting);i++)
                              {
                                      MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                                      MCUXFR_48_SSPI_TRIG=0xF8;
                                      MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
                                      MCUXFR_41_SSPI_WD1=(BYTE)(address);
                                      MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
                                      MCUXFR_43_SSPI_WD3=i;
                                      MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
                                      MCUXFR_48_SSPI_TRIG=0xFC;
                                      Delay1ms(10);
                              }
              
                              //  Write Protect
                              MCUXFR_40_SSPI_WD0=0x01;
                              MCUXFR_41_SSPI_WD1=0x0C;
                              MCUXFR_48_SSPI_TRIG=0xF9;
                      }
                      else
                      {
                              // SST flash
                              // 20051207 seven
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xc1;
              
                              // disable Write Protect
                              MCUXFR_40_SSPI_WD0=0x50;
                              MCUXFR_41_SSPI_WD1=0x01;
                              MCUXFR_42_SSPI_WD2=0x00;
C51 COMPILER V8.18   NVRAM                                                                 09/29/2009 23:58:03 PAGE 6   

                              MCUXFR_48_SSPI_TRIG=0xc8;
              
                              // Write Enable WREN + Sector Erase
                              MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                              MCUXFR_48_SSPI_TRIG=0xc1;
                              MCUXFR_40_SSPI_WD0=0x20; //  Sector Erase 0x00e000
                              MCUXFR_41_SSPI_WD1=(BYTE)(address);
                              MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
                              MCUXFR_43_SSPI_WD3=0x00;
                              MCUXFR_48_SSPI_TRIG=0xc4;
                              Delay1ms(25);  //from spec page 19
                              // WREN + Write Byte
                              for (i=0;i<sizeof(g_VideoSetting);i++)
                              {
                                      MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
                                      MCUXFR_48_SSPI_TRIG=0xc1;
                                      MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
                                      MCUXFR_41_SSPI_WD1=(BYTE)(address);
                                      MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
                                      MCUXFR_43_SSPI_WD3=i;
                                      MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
                                      MCUXFR_48_SSPI_TRIG=0xc5;
                                      Delay1ms(5);
                              }
              
                              // Enable Write Protect
                              MCUXFR_40_SSPI_WD0=0x50;
                              MCUXFR_41_SSPI_WD1=0x01;
                              MCUXFR_42_SSPI_WD2=0x0c;
                              MCUXFR_48_SSPI_TRIG=0xc8;
                  }
              }
              
              
              void mstSaveDisplayData(WORD address)
              {
                  mstSaveDisplayDataBanked(address);
                  Delay1ms(100);
                  mstSaveDisplayDataBanked(address+0x1000);
              }
              
              
              void mstLoadDisplayData(WORD address)
              {
                      BYTE i;
                      BYTE code *add;
                      add = address;
              
                      WatchDogClear();
                      //printf("\r\nRD<%x>",address);
              
                      for (i=0 ; i< sizeof(g_VideoSetting); i++)
                      {
                              *(&g_VideoSetting.ucVersion+ i) = *(add+i);
                      }
              
              }
              
              void NVRam_WriteByte(WORD addr, BYTE value)
              {
                       addr=addr;
                       value=value;
C51 COMPILER V8.18   NVRAM                                                                 09/29/2009 23:58:03 PAGE 7   

                       mstSaveDisplayData(SFD_ADDRESS);
              }
              
              void NVRam_WriteTbl(WORD addr, BYTE *buffer, WORD count)
              {
                       addr=addr;
                       buffer=buffer;
                       count=count;
                       mstSaveDisplayData(SFD_ADDRESS);
              }
              
              #endif


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    185    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----      30
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)