📄 m2_vsync2.lst
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C51 COMPILER V8.18 M2_VSYNC2 09/29/2009 23:58:05 PAGE 1
C51 COMPILER V8.18, COMPILATION OF MODULE M2_VSYNC2
OBJECT MODULE PLACED IN ..\..\1out\M2_VSync2.obj
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE ..\..\msLib\M2_VSync2.c BROWSE INCDIR(..\..\inc) DEBUG OBJECTEXTEND PRINT(.
-.\..\1out\M2_VSync2.lst) OBJECT(..\..\1out\M2_VSync2.obj)
line level source
1 #define MARIA2
2
3 #include "DSP_maria.H"
4 #include "dsprw.h"
5
6 #include "maria2_dsp_lib.h"
7
8 extern WORD XDATA g_wPreVpos;
9 extern WORD XDATA g_wFieldLineCuntPre;
10 extern XDATA WORD g_wFieldLineCunt;
11 extern WORD XDATA g_wField1LinesPre;
12 extern WORD XDATA g_wField2LinesPre;
13 extern XDATA WORD g_wField1Lines;
14 extern XDATA WORD g_wField2Lines;
15 extern BYTE xdata g_ucCuntPhaseV;
16 extern BYTE xdata g_ucCuntPhaseField;
17 extern BYTE xdata g_ucVstartTh;
18 extern BYTE idata g_ucUpdateVdebounce;
19 extern BYTE xdata g_ucVcrPauseCunt;
20 extern WORD xdata g_wVtotal[3];
21 extern WORD xdata g_wVtotalLatch;
22 extern WORD xdata g_wDetPhaseV[4];
23 extern BYTE xdata g_ucStableCunt;
24 extern BYTE xdata g_wVstartCnt;
25 extern BYTE xdata g_ucVstartTh;
26 extern BYTE xdata g_ucVcunt;
27 extern WORD xdata g_wStrbVcuntPre;
28 extern WORD xdata g_wStrbVcuntPreBak[2];
29 extern BYTE idata g_ucDebunceFieldErr;
30 extern BYTE xdata g_ucInterlaceCunt;
31 extern BYTE idata g_ucDSP_Ctl;
32 extern xdata BOOL g_bDSP_PhaseChange;
33 extern xdata BOOL g_bDSP_SupportTV;
34 extern WORD xdata g_wDefaultVTotal;
35
36 extern BYTE bdata V_Flag;
37 extern bit bVsyncReady;
38 extern bit bNonInter;
39 extern bit bVuseHW;
40
41 extern WORD xdata g_wVSyncHTotal;
42 extern bit g_bVdDsp_StopInt;
43
44 BYTE* VD_DSP_GetVersion(void)
45 {
46 1 return "M2 20060517";
47 1 }
48
49 void VD_VSync_SetHTotal( WORD wHTotal )
50 {
51 1 g_wVSyncHTotal = wHTotal;
52 1 }
53
54 // Default 656_setting:
C51 COMPILER V8.18 M2_VSYNC2 09/29/2009 23:58:05 PAGE 2
55 #define DSP_656_F_TGL_1_VAL 0x08
56 #define DSP_656_V_SET_1_VAL 0x10
57 #define DSP_656_V_CLR_1_VAL 0x12
58 #define DSP_656_F_TGL_2_VAL 0x08
59 #define DSP_656_V_SET_2_VAL 0x10
60 #define DSP_656_V_CLR_2_VAL 0x12
61
62 xdata BYTE g_ucVSync656FieldTgl;
63 xdata BYTE g_ucVSync656VSet;
64 xdata BYTE g_ucVSync656VClr;
65 void VD_Vsync_Set656VPosition( BYTE ucFieldTgl, BYTE ucVSet, BYTE ucVClr )
66 {
67 1 g_ucVSync656FieldTgl = ucFieldTgl;
68 1 g_ucVSync656VSet = ucVSet;
69 1 g_ucVSync656VClr = ucVClr;
70 1 }
71
72 void SetVthreshold(BYTE ucTh)
73 {
74 1 g_ucVstartTh = ucTh;
75 1 }
76
77 //*********************************************************
78 // InitVSYNC :
79 //*********************************************************
80 void initVSYNC(WORD wDefaultVTotal)
81 {
82 1 g_wVtotalLatch = wDefaultVTotal;
83 1 g_wVtotal[0] = g_wVtotal[1] = g_wVtotal[2] = wDefaultVTotal;
84 1
85 1 V_Flag = 0;
86 1 g_ucUpdateVdebounce = 0;
87 1 //Set656VS();
88 1
89 1 // mWriteDspRegW(0x8C, 0x10 - g_ucVsyncStart); // DSP_656_V_SET_1
90 1 // mWriteDspRegW(0x86, 0x08 - g_ucVsyncStart); // DSP_656_F_TGL_1
91 1 // mWriteDspRegW(0x90, 0x12 - g_ucVsyncStart); // DSP_656_V_CLR_1
92 1 // mWriteDspRegW(0x8E, 0x10 - g_ucVsyncStart); // DSP_656_V_SET_2
93 1 // mWriteDspRegW(0x88, 0x08 - g_ucVsyncStart); // DSP_656_F_TGL_2
94 1 // mWriteDspRegW(0x92, 0x12 - g_ucVsyncStart); // DSP_656_V_CLR_2
95 1 mWriteDspRegW(0x86, g_ucVSync656FieldTgl); // DSP_656_F_TGL_1
96 1 mWriteDspRegW(0x8C, g_ucVSync656VSet); // DSP_656_V_SET_1
97 1 mWriteDspRegW(0x90, g_ucVSync656VClr); // DSP_656_V_CLR_1
98 1 mWriteDspRegW(0x88, g_ucVSync656FieldTgl); // DSP_656_F_TGL_2
99 1 mWriteDspRegW(0x8E, g_ucVSync656VSet); // DSP_656_V_SET_2
100 1 mWriteDspRegW(0x92, g_ucVSync656VClr); // DSP_656_V_CLR_2
101 1
102 1 mWriteDspRegW(0x0e, 0x00f4);
103 1 mWriteDspRegW(V_Total, wDefaultVTotal);
104 1 g_ucVcrPauseCunt = 0;
105 1 g_wField1Lines = 0;
106 1 g_wField2Lines = 0;
107 1 bVsyncReady = 0;
108 1 bNonInter = 0;
109 1 g_ucUpdateVdebounce = 0;
110 1 mWriteDspRegW(VPLL_MODE2, 0x0347);
111 1
112 1 g_ucStableCunt = 0;
113 1 g_ucCuntPhaseField = 0;
114 1 g_ucCuntPhaseV = 0;
115 1 g_ucInterlaceCunt = 0;
116 1 g_wVstartCnt = 0;
C51 COMPILER V8.18 M2_VSYNC2 09/29/2009 23:58:05 PAGE 3
117 1 g_ucVcunt = 0;
118 1 bVuseHW = 0;
119 1 SetVthreshold(0xff);
120 1 }
121
122 void VD_DSP_Init(void)
123 {
124 1 g_bVdDsp_StopInt = 1;
125 1 g_ucDSP_Ctl = 0;
126 1
127 1 g_bDSP_PhaseChange = 0;
128 1
129 1 s_ucWriteIdx = 0;
130 1 s_ucReadIdx = 0;
131 1
132 1 g_bDSP_SupportTV = 1;
133 1 // g_ucVsyncStart = 0;
134 1
135 1 VD_Vsync_Set656VPosition( DSP_656_F_TGL_1_VAL, DSP_656_V_SET_1_VAL, DSP_656_V_CLR_1_VAL );
136 1
137 1 VD_DSP_GetVersion();
138 1
139 1 VD_VSync_SetHTotal( 858 );
140 1 }
141 void VD_DSP_Ctl( BYTE ucCtl, WORD wDefaultVTotal )
142 {
143 1 BYTE ucBank;
144 1 BYTE ucBk2_07;
145 1
146 1 g_bVdDsp_StopInt = 1; // function protect
147 1
148 1 g_ucDSP_Ctl = ucCtl;
149 1
150 1 ucBank = msReadByte( BK0_00 ); // Backup original bank
151 1 msWriteByte( BK0_00, REG_BANK2_VD );
152 1 ucBk2_07 = msReadByte( BK2_07 );
153 1
154 1
155 1 if( ucCtl&VD_DSP_CTL_ENABLE )
156 1 {
157 2 #ifdef MARIA2
158 2 mWriteDspRegW( DSP_10, msReadDspRegW(DSP_10)|0x0001 ); // SW v sycn
159 2 #endif
160 2 #ifdef MARIA3
mWriteDspRegW( DSP_10, msReadDspRegW(DSP_10)|0x0081 ); // SW v sync
#endif
163 2
164 2 //fFlagDSP = 0;
165 2
166 2 // Initialize V sync relative settings
167 2 g_wDefaultVTotal = wDefaultVTotal;
168 2 initVSYNC( wDefaultVTotal );
169 2
170 2 s_ucWriteIdx = 0;
171 2 s_ucReadIdx = 0;
172 2 }
173 1 else
174 1 {
175 2 #ifdef MARIA2
176 2 mWriteDspRegW( DSP_10, msReadDspRegW(DSP_10)&0xFFFE );
177 2 #endif
178 2 #ifdef MARIA3
C51 COMPILER V8.18 M2_VSYNC2 09/29/2009 23:58:05 PAGE 4
mWriteDspRegW( DSP_10, msReadDspRegW(DSP_10)&0xFF7E );
#endif
181 2 }
182 1
183 1 msWriteByte( BK2_07, ucBk2_07 );
184 1 msWriteByte( BK0_00, ucBank );
185 1
186 1 g_bVdDsp_StopInt = 0;
187 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 376 ----
CONSTANT SIZE = 12 ----
XDATA SIZE = 3 ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 6
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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