📄 c8051f930_defs.h.svn-base
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// 16-bit Register Definitions (might not be supported by all compilers)//-----------------------------------------------------------------------------SFR16 (DP, 0x82); // Data PointerSFR16 (TOFF, 0x85); // Temperature Sensor OffsetSFR16 (TMR3RL, 0x92); // Timer 3 ReloadSFR16 (TMR3, 0x94); // Timer 3 CounterSFR16 (ADC0, 0xBD); // ADC0 DataSFR16 (ADC0GT, 0xC3); // ADC0 Greater-Than CompareSFR16 (ADC0LT, 0xC5); // ADC0 Less-Than CompareSFR16 (TMR2RL, 0xCA); // Timer 2 ReloadSFR16 (TMR2, 0xCC); // Timer 2 CounterSFR16 (PCA0CP5, 0xD2); // PCA0 Module 5 Capture/CompareSFR16 (PCA0CP1, 0xE9); // PCA0 Module 1 Capture/CompareSFR16 (PCA0CP2, 0xEB); // PCA0 Module 2 Capture/CompareSFR16 (PCA0CP3, 0xED); // PCA0 Module 3 Capture/CompareSFR16 (PCA0, 0xF9); // PCA0 CounterSFR16 (PCA0CP0, 0xFB); // PCA0 Module 0 Capture/CompareSFR16 (PCA0CP4, 0xFD); // PCA0 Module 4 Capture/Compare//-----------------------------------------------------------------------------// Address Definitions for Bit-addressable Registers//-----------------------------------------------------------------------------#define SFR_P0 0x80#define SFR_TCON 0x88#define SFR_P1 0x90#define SFR_SCON0 0x98#define SFR_P2 0xA0#define SFR_IE 0xA8#define SFR_SPI1CN 0xB0#define SFR_IP 0xB8#define SFR_SMB0CN 0xC0#define SFR_TMR2CN 0xC8#define SFR_PSW 0xD0#define SFR_PCA0CN 0xD8#define SFR_ACC 0xE0#define SFR_ADC0CN 0xE8#define SFR_B 0xF0#define SFR_SPI0CN 0xF8//-----------------------------------------------------------------------------// Bit Definitions//-----------------------------------------------------------------------------// TCON 0x88SBIT (TF1, SFR_TCON, 7); // Timer 1 Overflow FlagSBIT (TR1, SFR_TCON, 6); // Timer 1 On/Off ControlSBIT (TF0, SFR_TCON, 5); // Timer 0 Overflow FlagSBIT (TR0, SFR_TCON, 4); // Timer 0 On/Off ControlSBIT (IE1, SFR_TCON, 3); // Ext. Interrupt 1 Edge FlagSBIT (IT1, SFR_TCON, 2); // Ext. Interrupt 1 TypeSBIT (IE0, SFR_TCON, 1); // Ext. Interrupt 0 Edge FlagSBIT (IT0, SFR_TCON, 0); // Ext. Interrupt 0 Type// SCON0 0x98SBIT (S0MODE, SFR_SCON0, 7); // UART0 Mode // Bit6 UNUSEDSBIT (MCE0, SFR_SCON0, 5); // UART0 MCESBIT (REN0, SFR_SCON0, 4); // UART0 RX EnableSBIT (TB80, SFR_SCON0, 3); // UART0 TX Bit 8SBIT (RB80, SFR_SCON0, 2); // UART0 RX Bit 8SBIT (TI0, SFR_SCON0, 1); // UART0 TX Interrupt FlagSBIT (RI0, SFR_SCON0, 0); // UART0 RX Interrupt Flag// IE 0xA8SBIT (EA, SFR_IE, 7); // Global Interrupt EnableSBIT (ESPI0, SFR_IE, 6); // SPI0 Interrupt EnableSBIT (ET2, SFR_IE, 5); // Timer 2 Interrupt EnableSBIT (ES0, SFR_IE, 4); // UART0 Interrupt EnableSBIT (ET1, SFR_IE, 3); // Timer 1 Interrupt EnableSBIT (EX1, SFR_IE, 2); // External Interrupt 1 EnableSBIT (ET0, SFR_IE, 1); // Timer 0 Interrupt EnableSBIT (EX0, SFR_IE, 0); // External Interrupt 0 Enable// SPI1CN 0xB0SBIT (SPIF1, SFR_SPI1CN, 7); // SPI1 Interrupt FlagSBIT (WCOL1, SFR_SPI1CN, 6); // SPI1 Write Collision FlagSBIT (MODF1, SFR_SPI1CN, 5); // SPI1 Mode Fault FlagSBIT (RXOVRN1, SFR_SPI1CN, 4); // SPI1 RX Overrun FlagSBIT (NSS1MD1, SFR_SPI1CN, 3); // SPI1 Slave Select Mode 1SBIT (NSS1MD0, SFR_SPI1CN, 2); // SPI1 Slave Select Mode 0SBIT (TXBMT1, SFR_SPI1CN, 1); // SPI1 TX Buffer Empty FlagSBIT (SPI1EN, SFR_SPI1CN, 0); // SPI1 Enable// IP 0xB8 // Bit7 UNUSEDSBIT (PSPI0, SFR_IP, 6); // SPI0 PrioritySBIT (PT2, SFR_IP, 5); // Timer 2 PrioritySBIT (PS0, SFR_IP, 4); // UART0 PrioritySBIT (PT1, SFR_IP, 3); // Timer 1 PrioritySBIT (PX1, SFR_IP, 2); // External Interrupt 1 PrioritySBIT (PT0, SFR_IP, 1); // Timer 0 PrioritySBIT (PX0, SFR_IP, 0); // External Interrupt 0 Priority// SMB0CN 0xC0SBIT (MASTER, SFR_SMB0CN, 7); // SMBus0 Master/SlaveSBIT (TXMODE, SFR_SMB0CN, 6); // SMBus0 Transmit ModeSBIT (STA, SFR_SMB0CN, 5); // SMBus0 Start FlagSBIT (STO, SFR_SMB0CN, 4); // SMBus0 Stop FlagSBIT (ACKRQ, SFR_SMB0CN, 3); // SMBus0 Acknowledge RequestSBIT (ARBLOST, SFR_SMB0CN, 2); // SMBus0 Arbitration LostSBIT (ACK, SFR_SMB0CN, 1); // SMBus0 Acknowledge FlagSBIT (SI, SFR_SMB0CN, 0); // SMBus0 Interrupt Pending Flag// TMR2CN 0xC8SBIT (TF2H, SFR_TMR2CN, 7); // Timer 2 High Byte Overflow FlagSBIT (TF2L, SFR_TMR2CN, 6); // Timer 2 Low Byte Overflow FlagSBIT (TF2LEN, SFR_TMR2CN, 5); // Timer 2 Low Byte Interrupt EnableSBIT (TF2CEN, SFR_TMR2CN, 4); // Timer 2 Lfo Capture EnableSBIT (T2SPLIT, SFR_TMR2CN, 3); // Timer 2 Split Mode EnableSBIT (TR2, SFR_TMR2CN, 2); // Timer 2 On/Off ControlSBIT (T2RCLK, SFR_TMR2CN, 1); // Timer 2 Capture ModeSBIT (T2XCLK, SFR_TMR2CN, 0); // Timer 2 External Clock Select// PSW 0xD0SBIT (CY, SFR_PSW, 7); // Carry FlagSBIT (AC, SFR_PSW, 6); // Auxiliary Carry FlagSBIT (F0, SFR_PSW, 5); // User Flag 0SBIT (RS1, SFR_PSW, 4); // Register Bank Select 1SBIT (RS0, SFR_PSW, 3); // Register Bank Select 0SBIT (OV, SFR_PSW, 2); // Overflow FlagSBIT (F1, SFR_PSW, 1); // User Flag 1SBIT (P, SFR_PSW, 0); // Accumulator Parity Flag// PCA0CN 0xD8SBIT (CF, SFR_PCA0CN, 7); // PCA0 Counter Overflow FlagSBIT (CR, SFR_PCA0CN, 6); // PCA0 Counter Run Control BitSBIT (CCF5, SFR_PCA0CN, 5); // PCA0 Module 5 Interrupt FlagSBIT (CCF4, SFR_PCA0CN, 4); // PCA0 Module 4 Interrupt FlagSBIT (CCF3, SFR_PCA0CN, 3); // PCA0 Module 3 Interrupt FlagSBIT (CCF2, SFR_PCA0CN, 2); // PCA0 Module 2 Interrupt FlagSBIT (CCF1, SFR_PCA0CN, 1); // PCA0 Module 1 Interrupt FlagSBIT (CCF0, SFR_PCA0CN, 0); // PCA0 Module 0 Interrupt Flag// ADC0CN 0xE8SBIT (AD0EN, SFR_ADC0CN, 7); // ADC0 EnableSBIT (BURSTEN, SFR_ADC0CN, 6); // ADC0 Burst EnableSBIT (AD0INT, SFR_ADC0CN, 5); // ADC0 EOC Interrupt FlagSBIT (AD0BUSY, SFR_ADC0CN, 4); // ADC0 Busy FlagSBIT (AD0WINT, SFR_ADC0CN, 3); // ADC0 Window Interrupt FlagSBIT (AD0CM2, SFR_ADC0CN, 2); // ADC0 Convert Start Mode Bit 2SBIT (AD0CM1, SFR_ADC0CN, 1); // ADC0 Convert Start Mode Bit 1SBIT (AD0CM0, SFR_ADC0CN, 0); // ADC0 Convert Start Mode Bit 0// SPI0CN 0xF8SBIT (SPIF0, SFR_SPI0CN, 7); // SPI0 Interrupt FlagSBIT (WCOL0, SFR_SPI0CN, 6); // SPI0 Write Collision FlagSBIT (MODF0, SFR_SPI0CN, 5); // SPI0 Mode Fault FlagSBIT (RXOVRN0, SFR_SPI0CN, 4); // SPI0 RX Overrun FlagSBIT (NSS0MD1, SFR_SPI0CN, 3); // SPI0 Slave Select Mode 1SBIT (NSS0MD0, SFR_SPI0CN, 2); // SPI0 Slave Select Mode 0SBIT (TXBMT0, SFR_SPI0CN, 1); // SPI0 TX Buffer Empty FlagSBIT (SPI0EN, SFR_SPI0CN, 0); // SPI0 Enable//-----------------------------------------------------------------------------// Interrupt Priorities//-----------------------------------------------------------------------------#define INTERRUPT_INT0 0 // External Interrupt 0#define INTERRUPT_TIMER0 1 // Timer0 Overflow#define INTERRUPT_INT1 2 // External Interrupt 1#define INTERRUPT_TIMER1 3 // Timer1 Overflow#define INTERRUPT_UART0 4 // Serial Port 0#define INTERRUPT_TIMER2 5 // Timer2 Overflow#define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0#define INTERRUPT_SMBUS0 7 // SMBus0 Interface#define INTERRUPT_RTC0ALARM 8 // RTC0 (SmaRTClock) Alarm#define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison#define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion#define INTERRUPT_PCA0 11 // PCA0 Peripheral#define INTERRUPT_COMPARATOR0 12 // Comparator0#define INTERRUPT_COMPARATOR1 13 // Comparator1#define INTERRUPT_TIMER3 14 // Timer3 Overflow#define INTERRUPT_VDDMON 15 // VDD Monitor Early Warning#define INTERRUPT_PORT_MATCH 16 // Port Match#define INTERRUPT_RTC0_OSC_FAIL 17 // RTC0 (smaRTClock) Osc. Fail#define INTERRUPT_SPI1 18 // Serial Peripheral Interface 1//-----------------------------------------------------------------------------// SFR Page Definitions//-----------------------------------------------------------------------------#define CONFIG_PAGE 0x0F // SYSTEM AND PORT CONFIGURATION PAGE#define LEGACY_PAGE 0x00 // LEGACY SFR PAGE#define CRC0_PAGE 0x0F // CRC0#define TOFF_PAGE 0x0F // TEMPERATURE SENSOR OFFSET PAGE//-----------------------------------------------------------------------------// Header File PreProcessor Directive//-----------------------------------------------------------------------------#endif // #define C8051F930_DEFS_H//-----------------------------------------------------------------------------// End Of File//-----------------------------------------------------------------------------⌨️ 快捷键说明
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