📄 c8051f930_defs.h.svn-base
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//-----------------------------------------------------------------------------// C8051F930_defs.h//-----------------------------------------------------------------------------// Copyright 2007 Silicon Laboratories, Inc.// http://www.silabs.com//// Program Description://// Register/bit definitions for the C8051F93x/2x family.////// FID:// Target: C8051F93x/2x// Tool chain: Keil, SDCC// Command Line: None//// Release 1.4// - Added definitions for ONESHOT and FLSCL.// - 4 OCT 2007 (FB)//// Release 1.3// - Switched the addresses of DC0CF and DC0CN.// - 20 SEP 2007 (FB)//// Release 1.2// - Moved SPI1 to interrupt 18 and inserted smaRTClock Osc Fail in its// original place.// - SPI1 bit-addressable SFRs corrected to point at the correct address.// - 7 SEP 2007 (FB, errors found by KAB)//// Release 1.1// -Corrected ADC0TK address from 0xBC to 0xBD // - 15 AUG 2007 (FB)//// Release 1.0// -Ported from 'F41x DEFS rev 1.0 by FB// -7 JUNE 2007////-----------------------------------------------------------------------------// Header File Preprocessor Directive//-----------------------------------------------------------------------------#ifndef C8051F930_DEFS_H#define C8051F930_DEFS_H#include <compiler_defs.h>//-----------------------------------------------------------------------------// Byte Registers//-----------------------------------------------------------------------------SFR (P0, 0x80); // Port 0 LatchSFR (SP, 0x81); // Stack PointerSFR (DPL, 0x82); // Data Pointer LowSFR (DPH, 0x83); // Data Pointer HighSFR (SPI1CFG, 0x84); // SPI1 ConfigurationSFR (SPI1CKR, 0x85); // SPI1 Clock Rate ControlSFR (TOFFL, 0x85); // Temperature Offset LowSFR (SPI1DAT, 0x86); // SPI1 DataSFR (TOFFH, 0x86); // Temperature Offset HighSFR (PCON, 0x87); // Power ControlSFR (TCON, 0x88); // Timer/Counter ControlSFR (TMOD, 0x89); // Timer/Counter ModeSFR (TL0, 0x8A); // Timer/Counter 0 LowSFR (TL1, 0x8B); // Timer/Counter 1 LowSFR (TH0, 0x8C); // Timer/Counter 0 HighSFR (TH1, 0x8D); // Timer/Counter 1 HighSFR (CKCON, 0x8E); // Clock ControlSFR (PSCTL, 0x8F); // Program Store R/W ControlSFR (P1, 0x90); // Port 1 LatchSFR (TMR3CN, 0x91); // Timer/Counter 3 ControlSFR (CRC0DAT, 0x91); // CRC0 DataSFR (TMR3RLL, 0x92); // Timer/Counter 3 Reload LowSFR (CRC0CN, 0x92); // CRC0 ControlSFR (TMR3RLH, 0x93); // Timer/Counter 3 Reload HighSFR (CRC0IN, 0x93); // CRC0 InputSFR (TMR3L, 0x94); // Timer/Counter 3 LowSFR (CRC0FLIP, 0x94); // CRC0 FlipSFR (TMR3H, 0x95); // Timer/Counter 3 HighSFR (DC0CF, 0x96); // DC0 (DC/DC Converter) ConfigurationSFR (CRC0AUTO, 0x96); // CRC0 Automatic ControlSFR (DC0CN, 0x97); // DC0 (DC/DC Converter) ControlSFR (CRC0CNT, 0x97); // CRC0 Automatic Flash Sector CountSFR (SCON0, 0x98); // UART0 ControlSFR (SBUF0, 0x99); // UART0 Data BufferSFR (CPT1CN, 0x9A); // Comparator1 ControlSFR (CPT0CN, 0x9B); // Comparator0 ControlSFR (CPT1MD, 0x9C); // Comparator1 Mode SelectionSFR (CPT0MD, 0x9D); // Comparator0 Mode SelectionSFR (CPT1MX, 0x9E); // Comparator1 Mux SelectionSFR (CPT0MX, 0x9F); // Comparator0 Mux SelectionSFR (P2, 0xA0); // Port 2 LatchSFR (SPI0CFG, 0xA1); // SPI0 ConfigurationSFR (SPI0CKR, 0xA2); // SPI0 Clock Rate ControlSFR (SPI0DAT, 0xA3); // SPI0 DataSFR (P0MDOUT, 0xA4); // Port 0 Output Mode ConfigurationSFR (P0DRV, 0xA4); // Port 0 Drive StrengthSFR (P1MDOUT, 0xA5); // Port 1 Output Mode ConfigurationSFR (P1DRV, 0xA5); // Port 1 Drive StrengthSFR (P2MDOUT, 0xA6); // Port 2 Output Mode ConfigurationSFR (P2DRV, 0xA6); // Port 2 Drive StrengthSFR (SFRPAGE, 0xA7); // SFR PageSFR (IE, 0xA8); // Interrupt EnableSFR (CLKSEL, 0xA9); // Clock SelectSFR (EMI0CN, 0xAA); // EMIF ControlSFR (EMI0CF, 0xAB); // EMIF ConfigurationSFR (RTC0ADR, 0xAC); // RTC0 AddressSFR (RTC0DAT, 0xAD); // RTC0 DataSFR (RTC0KEY, 0xAE); // RTC0 KeySFR (EMI0TC, 0xAF); // EMIF Timing ControlSFR (ONESHOT, 0xAF); // ONESHOT Timing ControlSFR (SPI1CN, 0xB0); // SPI1 ControlSFR (OSCXCN, 0xB1); // External Oscillator ControlSFR (OSCICN, 0xB2); // Internal Oscillator ControlSFR (OSCICL, 0xB3); // Internal Oscillator CalibrationSFR (PMU0CF, 0xB5); // PMU0 ConfigurationSFR (FLSCL, 0xB6); // Flash Scale RegisterSFR (FLKEY, 0xB7); // Flash Lock And KeySFR (IP, 0xB8); // Interrupt PrioritySFR (IREF0CN, 0xB9); // Current Reference IREF0 ControlSFR (ADC0AC, 0xBA); // ADC0 Accumulator ConfigurationSFR (ADC0PWR, 0xBA); // ADC0 Burst Mode Power-Up TimeSFR (ADC0MX, 0xBB); // AMUX0 Channel SelectSFR (ADC0CF, 0xBC); // ADC0 ConfigurationSFR (ADC0TK, 0xBD); // ADC0 Tracking ControlSFR (ADC0L, 0xBD); // ADC0 LowSFR (ADC0H, 0xBE); // ADC0 HighSFR (P1MASK, 0xBF); // Port 1 MaskSFR (SMB0CN, 0xC0); // SMBus0 ControlSFR (SMB0CF, 0xC1); // SMBus0 ConfigurationSFR (SMB0DAT, 0xC2); // SMBus0 DataSFR (ADC0GTL, 0xC3); // ADC0 Greater-Than Compare LowSFR (ADC0GTH, 0xC4); // ADC0 Greater-Than Compare HighSFR (ADC0LTL, 0xC5); // ADC0 Less-Than Compare Word LowSFR (ADC0LTH, 0xC6); // ADC0 Less-Than Compare Word HighSFR (P0MASK, 0xC7); // Port 0 MaskSFR (TMR2CN, 0xC8); // Timer/Counter 2 ControlSFR (REG0CN, 0xC9); // Voltage Regulator (REG0) ControlSFR (TMR2RLL, 0xCA); // Timer/Counter 2 Reload LowSFR (TMR2RLH, 0xCB); // Timer/Counter 2 Reload HighSFR (TMR2L, 0xCC); // Timer/Counter 2 LowSFR (TMR2H, 0xCD); // Timer/Counter 2 HighSFR (PCA0CPM5, 0xCE); // PCA0 Module 5 Mode RegisterSFR (P1MAT, 0xCF); // Port 1 MatchSFR (PSW, 0xD0); // Program Status WordSFR (REF0CN, 0xD1); // Voltage Reference ControlSFR (PCA0CPL5, 0xD2); // PCA0 Capture 5 LowSFR (PCA0CPH5, 0xD3); // PCA0 Capture 5 HighSFR (P0SKIP, 0xD4); // Port 0 SkipSFR (P1SKIP, 0xD5); // Port 1 SkipSFR (P2SKIP, 0xD6); // Port 2 SkipSFR (P0MAT, 0xD7); // Port 0 MatchSFR (PCA0CN, 0xD8); // PCA0 ControlSFR (PCA0MD, 0xD9); // PCA0 ModeSFR (PCA0CPM0, 0xDA); // PCA0 Module 0 Mode RegisterSFR (PCA0CPM1, 0xDB); // PCA0 Module 1 Mode RegisterSFR (PCA0CPM2, 0xDC); // PCA0 Module 2 Mode RegisterSFR (PCA0CPM3, 0xDD); // PCA0 Module 3 Mode RegisterSFR (PCA0CPM4, 0xDE); // PCA0 Module 4 Mode RegisterSFR (PCA0PWM, 0xDF); // PCA0 PWM ConfigurationSFR (ACC, 0xE0); // AccumulatorSFR (XBR0, 0xE1); // Port I/O Crossbar Control 0SFR (XBR1, 0xE2); // Port I/O Crossbar Control 1SFR (XBR2, 0xE3); // Port I/O Crossbar Control 2SFR (IT01CF, 0xE4); // INT0/INT1 ConfigurationSFR (EIE1, 0xE6); // Extended Interrupt Enable 1SFR (EIE2, 0xE7); // Extended Interrupt Enable 2SFR (ADC0CN, 0xE8); // ADC0 ControlSFR (PCA0CPL1, 0xE9); // PCA0 Capture 1 LowSFR (PCA0CPH1, 0xEA); // PCA0 Capture 1 HighSFR (PCA0CPL2, 0xEB); // PCA0 Capture 2 LowSFR (PCA0CPH2, 0xEC); // PCA0 Capture 2 HighSFR (PCA0CPL3, 0xED); // PCA0 Capture 3 LowSFR (PCA0CPH3, 0xEE); // PCA0 Capture 3 HighSFR (RSTSRC, 0xEF); // Reset Source Configuration/StatusSFR (B, 0xF0); // B RegisterSFR (P0MDIN, 0xF1); // Port 0 Input Mode ConfigurationSFR (P1MDIN, 0xF2); // Port 1 Input Mode ConfigurationSFR (P2MDIN, 0xF3); // Port 2 Input Mode ConfigurationSFR (SMB0ADR, 0xF4); // SMBus Slave AddressSFR (SMB0ADM, 0xF5); // SMBus Slave Address MaskSFR (EIP1, 0xF6); // Extended Interrupt Priority 1SFR (EIP2, 0xF7); // Extended Interrupt Priority 2SFR (SPI0CN, 0xF8); // SPI0 ControlSFR (PCA0L, 0xF9); // PCA0 Counter LowSFR (PCA0H, 0xFA); // PCA0 Counter HighSFR (PCA0CPL0, 0xFB); // PCA0 Capture 0 LowSFR (PCA0CPH0, 0xFC); // PCA0 Capture 0 HighSFR (PCA0CPL4, 0xFD); // PCA0 Capture 4 LowSFR (PCA0CPH4, 0xFE); // PCA0 Capture 4 HighSFR (VDM0CN, 0xFF); // VDD Monitor Control//-----------------------------------------------------------------------------⌨️ 快捷键说明
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