125m_dds.drc

ProtelDXP100.rar

Protel Design System Design Rule Check
PCB File : \DOC\Draft\work\95  AD9850\125M_DDS.PcbDoc
Date     : 2004-7-22
Time     : 2:54:55

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=30mil) (Preferred=15mil) (All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=5mil) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
   Violation         Net VDD   is broken into 3 sub-nets. Routed To 50.00%
     Subnet : C1-2     U1-6     
     Subnet : U1-23    C2-2     
     Subnet : JP3-5    
   Violation         Net GND   is broken into 16 sub-nets. Routed To 0.00%
     Subnet : R7-2     
     Subnet : C4-1     
     Subnet : R3-1     
     Subnet : R8-2     
     Subnet : U1-10    
     Subnet : C3-1     
     Subnet : U1-19    
     Subnet : JP3-2    
     Subnet : P1-1     
     Subnet : C8-1     
     Subnet : P1-2     
     Subnet : P1-2     
     Subnet : C7-1     
     Subnet : R4-1     
     Subnet : C6-1     
     Subnet : C9-1     
   Violation         Net DGND   is broken into 5 sub-nets. Routed To 0.00%
     Subnet : C1-1     
     Subnet : U1-5     
     Subnet : C2-1     
     Subnet : U1-24    
     Subnet : JP3-4    
   Violation         Net VCC   is broken into 3 sub-nets. Routed To 66.67%
     Subnet : C3-2     U1-11    U1-18    C4-2     
     Subnet : U2-8     C6-2     
     Subnet : JP3-3    
Rule Violations :4

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0


Violations Detected : 4
Time Elapsed        : 00:00:00