01-继电器控制试验（节点2）.plg

来自「CAN现场总线.rar」· PLG 代码 · 共 640 行

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640 行
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Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c....\01-继电器控制试验（节点2）.C(158): error C202: 'Relay_Flag': undefined identifier.\01-继电器控制试验（节点2）.C(170): error C202: 'Relay_Flag': undefined identifier.\01-继电器控制试验（节点2）.C(171): error C202: 'Relay_Flag': undefined identifierTarget not createdBuild target 'Target 1'compiling 01-继电器控制试验（节点2）.c....\01-继电器控制试验（节点2）.C(158): error C202: 'Relay_Flag': undefined identifier.\01-继电器控制试验（节点2）.C(170): error C202: 'Relay_Flag': undefined identifier.\01-继电器控制试验（节点2）.C(171): error C202: 'Relay_Flag': undefined identifierTarget not createdBuild target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE10H    TO:      FE10H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE11H    TO:      FE11H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE12H    TO:      FE12H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE13H    TO:      FE13H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE14H    TO:      FE14H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE15H    TO:      FE15H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE16H    TO:      FE16H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE17H    TO:      FE17H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE18H    TO:      FE18H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE19H    TO:      FE19H*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1AH    TO:      FE1AH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1BH    TO:      FE1BH*** WARNING L6: XDATA SPACE MEMORY OVERLAP    FROM:    FE1CH    TO:      FE1CHcreating hex file from "01-继电器控制试验（节点2）"..."01-继电器控制试验（节点2）" - 0 Error(s), 21 Warning(s).Build target 'Target 1'compiling 01-继电器控制试验（节点2）.c...linking...*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS    SEGMENT: ?PR?CHECK_RELAY?01____鏮鱛______椋__赺

01-继电器控制试验（节点2）.plg - 源码说明

本页面展示了「CAN现场总线.rar」中的 01-继电器控制试验（节点2）.plg 源码文件，采用 PLG 编程语言编写，共 640 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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