can_top_translate.vhd

USB_I2C_MAC_FPGA_Code.rar

-- Xilinx Vhdl netlist produced by netgen application (version G.23)
-- Command       : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim can_top.ngd can_top_translate.vhd 
-- Input file    : can_top.ngd
-- Output file   : can_top_translate.vhd
-- Design name   : can_top
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 2s300epq208-6

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity can_top is
  port (
    rst_i : in STD_LOGIC := 'X'; 
    rx_i : in STD_LOGIC := 'X'; 
    ale_i : in STD_LOGIC := 'X'; 
    clk_i : in STD_LOGIC := 'X'; 
    rd_i : in STD_LOGIC := 'X'; 
    wr_i : in STD_LOGIC := 'X'; 
    cs_can_i : in STD_LOGIC := 'X'; 
    tx_o : out STD_LOGIC; 
    irq_on : out STD_LOGIC; 
    clkout_o : out STD_LOGIC; 
    port_0_io : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end can_top;

architecture Structure of can_top is
  signal rst_i_IBUF : STD_LOGIC; 
  signal rx_i_IBUF : STD_LOGIC; 
  signal ale_i_IBUF : STD_LOGIC; 
  signal clk_i_BUFGP : STD_LOGIC; 
  signal irq_on_OBUF : STD_LOGIC; 
  signal rd_i_IBUF : STD_LOGIC; 
  signal wr_i_IBUF : STD_LOGIC; 
  signal cs_can_i_IBUF : STD_LOGIC; 
  signal clkout_o_OBUF : STD_LOGIC; 
  signal tx_successful : STD_LOGIC; 
  signal i_can_bsp_node_bus_off : STD_LOGIC; 
  signal we_tx_err_cnt : STD_LOGIC; 
  signal last_bit_of_inter : STD_LOGIC; 
  signal wr_i_q : STD_LOGIC; 
  signal i_can_btl_sample_point : STD_LOGIC; 
  signal overrun : STD_LOGIC; 
  signal read_error_code_capture_reg : STD_LOGIC; 
  signal error_status : STD_LOGIC; 
  signal cs : STD_LOGIC; 
  signal i_can_btl_sampled_bit : STD_LOGIC; 
  signal listen_only_mode : STD_LOGIC; 
  signal Q_n0000 : STD_LOGIC; 
  signal tx_point : STD_LOGIC; 
  signal N23149 : STD_LOGIC; 
  signal N23151 : STD_LOGIC; 
  signal i_can_bsp_i_can_crc_rx_n0000_8_Q : STD_LOGIC; 
  signal I8_N3072 : STD_LOGIC; 
  signal i_can_bsp_i_can_crc_rx_n0000_3_Q : STD_LOGIC; 
  signal set_reset_mode : STD_LOGIC; 
  signal i_can_bsp_i_can_crc_rx_n0000_4_Q : STD_LOGIC; 
  signal acceptance_filter_mode : STD_LOGIC; 
  signal i_can_bsp_tx : STD_LOGIC; 
  signal N54651 : STD_LOGIC; 
  signal N54653 : STD_LOGIC; 
  signal data_out_fifo_selected : STD_LOGIC; 
  signal i_can_bsp_transmitting : STD_LOGIC; 
  signal i_can_bsp_rx_idle : STD_LOGIC; 
  signal read_arbitration_lost_capture_reg : STD_LOGIC; 
  signal i_can_bsp_node_error_passive : STD_LOGIC; 
  signal i_can_bsp_need_to_tx : STD_LOGIC; 
  signal N55708 : STD_LOGIC; 
  signal i_can_registers_single_shot_transmission : STD_LOGIC; 
  signal info_empty : STD_LOGIC; 
  signal i_can_bsp_i_can_crc_rx_n0000_14_Q : STD_LOGIC; 
  signal i_can_bsp_i_can_crc_rx_n0000_10_Q : STD_LOGIC; 
  signal i_can_bsp_Mmux_n0005_net177 : STD_LOGIC; 
  signal rd_i_q : STD_LOGIC; 
  signal i_can_bsp_i_can_crc_rx_n0000_7_Q : STD_LOGIC; 
  signal i_can_btl_sampled_bit_q : STD_LOGIC; 
  signal abort_tx : STD_LOGIC; 
  signal hard_sync : STD_LOGIC; 
  signal i_can_bsp_arbitration_lost_capture_31 : STD_LOGIC; 
  signal i_can_bsp_arbitration_lost_capture_30 : STD_LOGIC; 
  signal i_can_bsp_arbitration_lost_capture_29 : STD_LOGIC; 
  signal i_can_bsp_arbitration_lost_capture_28 : STD_LOGIC; 
  signal i_can_bsp_arbitration_lost_capture_27 : STD_LOGIC; 
  signal i_can_btl_clk_en : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0035_inst_lut4_10 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0035_inst_cy_87 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_84 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_9 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_54 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_15 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_48 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_78 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_8 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_77 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_16 : STD_LOGIC; 
  signal i_can_btl_resync : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_85 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_55 : STD_LOGIC; 
  signal i_can_btl_sync_blocked : STD_LOGIC; 
  signal i_can_btl_resync_latched : STD_LOGIC; 
  signal i_can_btl_clk_cnt_15 : STD_LOGIC; 
  signal i_can_btl_seg1 : STD_LOGIC; 
  signal i_can_btl_n0007 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_16 : STD_LOGIC; 
  signal i_can_btl_n0021 : STD_LOGIC; 
  signal i_can_btl_n0017 : STD_LOGIC; 
  signal i_can_btl_n0030 : STD_LOGIC; 
  signal i_can_btl_N28750 : STD_LOGIC; 
  signal i_can_btl_n0033 : STD_LOGIC; 
  signal i_can_btl_n0028 : STD_LOGIC; 
  signal i_can_btl_n0034 : STD_LOGIC; 
  signal i_can_btl_n0029 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_10 : STD_LOGIC; 
  signal i_can_btl_n0035 : STD_LOGIC; 
  signal i_can_btl_n0041 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0035_inst_lut4_13 : STD_LOGIC; 
  signal i_can_btl_n0042 : STD_LOGIC; 
  signal i_can_btl_N28740 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_12 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_56 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_12 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0035_inst_lut4_12 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_80 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_50 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_53 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_11 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_14 : STD_LOGIC; 
  signal i_can_btl_seg2 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_82 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_81 : STD_LOGIC; 
  signal i_can_btl_sync_window : STD_LOGIC; 
  signal i_can_btl_go_seg2 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_51 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_52 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_10 : STD_LOGIC; 
  signal i_can_btl_go_seg1 : STD_LOGIC; 
  signal i_can_btl_resync_blocked : STD_LOGIC; 
  signal i_can_btl_sync : STD_LOGIC; 
  signal i_can_btl_clk_cnt_13 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_lut3_13 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_14 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_83 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0035_inst_cy_89 : STD_LOGIC; 
  signal i_can_btl_n0074 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_11 : STD_LOGIC; 
  signal i_can_btl_n0080 : STD_LOGIC; 
  signal i_can_btl_n0075 : STD_LOGIC; 
  signal i_can_btl_n0081 : STD_LOGIC; 
  signal i_can_btl_n0076 : STD_LOGIC; 
  signal i_can_btl_n0082 : STD_LOGIC; 
  signal i_can_btl_n0077 : STD_LOGIC; 
  signal i_can_btl_n0083 : STD_LOGIC; 
  signal i_can_btl_n0078 : STD_LOGIC; 
  signal i_can_btl_n0084 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_9 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_cy_79 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0034_inst_cy_87 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_lut4_0 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0034_inst_cy_88 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_lut4_3 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_cy_9 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_lut4_2 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_cy_8 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_lut4_1 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0042_inst_cy_7 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_cy_7 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_lut4_0 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_lut4_3 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_cy_9 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_lut4_2 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_cy_8 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0041_inst_lut4_1 : STD_LOGIC; 
  signal i_can_btl_Madd_n0038_inst_cy_12 : STD_LOGIC; 
  signal i_can_btl_Madd_n0038_inst_cy_13 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0034_inst_lut4_11 : STD_LOGIC; 
  signal i_can_btl_Madd_n0038_inst_cy_11 : STD_LOGIC; 
  signal i_can_btl_Madd_n0038_inst_lut2_6 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_15 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_10 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_17 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_21 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_16 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_20 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_15 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_19 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_14 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_18 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_13 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_17 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_12 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_cy_16 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0030_inst_lut2_11 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_cy_23 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_lut4_4 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_lut4_9 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_cy_27 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_lut4_8 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_cy_26 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_lut4_7 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_cy_25 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_lut4_6 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_cy_24 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0007_inst_lut4_5 : STD_LOGIC; 
  signal i_can_btl_Madd_n0045_inst_cy_31 : STD_LOGIC; 
  signal i_can_btl_Madd_n0045_inst_cy_30 : STD_LOGIC; 
  signal i_can_btl_Madd_n0045_inst_cy_32 : STD_LOGIC; 
  signal i_can_btl_Madd_n0045_inst_cy_33 : STD_LOGIC; 
  signal i_can_btl_Madd_n0045_inst_cy_29 : STD_LOGIC; 
  signal i_can_btl_Madd_n0045_inst_lut2_18 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_35 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_24 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_33 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_43 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_32 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_42 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_31 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_41 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_30 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_40 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_29 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_39 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_28 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_38 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_27 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_37 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_26 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_cy_36 : STD_LOGIC; 
  signal i_can_btl_Mcompar_sync_window_inst_lut2_25 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_41 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_50 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_39 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_52 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_49 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_38 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_51 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_48 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_37 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_47 : STD_LOGIC; 
  signal i_can_btl_clk_cnt_inst_sum_49 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_34 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_45 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_40 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_35 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_cy_46 : STD_LOGIC; 
  signal i_can_btl_Mcompar_n0034_inst_lut4_12 : STD_LOGIC; 
  signal i_can_btl_Msub_n0003_inst_lut2_36 : STD_LOGIC; 
  signal i_can_btl_Madd_n0044_inst_cy_55 : STD_LOGIC; 
  signal i_can_btl_Madd_n0044_inst_lut2_46 : STD_LOGIC; 
  signal i_can_btl_Madd_n0044_inst_cy_56 : STD_LOGIC;