📄 can_testbench.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005
##
vlib work
vlog can_register_asyn_syn.v
vlog can_register_asyn.v
vlog can_register.v
vlog can_registers.v
vlog can_btl.v
vlog can_crc.v
vlog can_acf.v
vlog can_fifo.v
vlog can_ibo.v
vlog can_bsp.v
vlog can_top.v
vlog can_testbench.v
vlog C:/Program Files/Xilinx/verilog/src/glbl.v
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver -lib work can_testbench glbl
do can_testbench.udo
view wave
add wave *
view structure
view signals
run 1000ns
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