📄 can_testbench.v
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// Enabling IRQ's (extended mode)
write_register(8'd4, 8'hff);
fork
begin
#2700;
$display("\n\nStart receiving data from CAN bus");
/* Standard frame format
receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h1, 15'h2d9c); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h2, 15'h46b4); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h0, 15'h42cd); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h1, 15'h555f); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h2, 15'h6742); // mode, rtr, id, length, crc
*/
// Extended frame format
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h0, 15'h23aa); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
end
begin
tx_request_command;
end
begin
// Transmitting acknowledge
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
#1 rx = 0;
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
#1 rx = 1;
end
begin // Reading irq and arbitration lost capture register
repeat(1)
begin
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
begin
@ (posedge clk);
end
// Read irq register
#1 read_register(8'd3);
// Read arbitration lost capture register
read_register(8'd11);
end
repeat(1)
begin
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
begin
@ (posedge clk);
end
// Read irq register
#1 read_register(8'd3);
end
repeat(1)
begin
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
begin
@ (posedge clk);
end
// Read arbitration lost capture register
read_register(8'd11);
end
end
join
read_receive_buffer;
release_rx_buffer_command;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
#200000;
read_receive_buffer;
// Read irq register
read_register(8'd3);
#1000;
end
endtask // send_frame_extended
task self_reception_request; // CAN IP core sends sets self reception mode and transmits a msg. This test runs in EXTENDED mode
begin
// Switch-on reset mode
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
// Set Clock Divider register
extended_mode = 1'b1;
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
// Set Acceptance Code and Acceptance Mask registers
write_register(8'd16, 8'ha6); // acceptance code 0
write_register(8'd17, 8'hb0); // acceptance code 1
write_register(8'd18, 8'h12); // acceptance code 2
write_register(8'd19, 8'h30); // acceptance code 3
write_register(8'd20, 8'h00); // acceptance mask 0
write_register(8'd21, 8'h00); // acceptance mask 1
write_register(8'd22, 8'h00); // acceptance mask 2
write_register(8'd23, 8'h00); // acceptance mask 3
// Setting the "self test mode"
write_register(8'd0, 8'h4);
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
// After exiting the reset mode sending bus free
repeat (11) send_bit(1);
// Writing TX frame information + identifier + data
write_register(8'd16, 8'h45); // Frame format = 0, Remote transmision request = 1, DLC = 5
write_register(8'd17, 8'ha6); // ID[28:21] = a6
write_register(8'd18, 8'ha0); // ID[20:18] = 5
// write_register(8'd19, 8'h78); RTR does not send any data
// write_register(8'd20, 8'h9a);
// write_register(8'd21, 8'hbc);
// write_register(8'd22, 8'hde);
// write_register(8'd23, 8'hf0);
// write_register(8'd24, 8'h0f);
// write_register(8'd25, 8'hed);
// write_register(8'd26, 8'hcb);
// write_register(8'd27, 8'ha9);
// write_register(8'd28, 8'h87);
// Enabling IRQ's (extended mode)
write_register(8'd4, 8'hff);
self_reception_request_command;
#400000;
read_receive_buffer;
release_rx_buffer_command;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
read_receive_buffer;
// Read irq register
read_register(8'd3);
#1000;
end
endtask // self_reception_request
task test_empty_fifo;
begin
// Enable irqs (basic mode)
write_register(8'd0, 8'h1e);
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
end
endtask
task test_empty_fifo_ext;
begin
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
end
endtask
task test_full_fifo;
begin
// Enable irqs (basic mode)
write_register(8'd0, 8'h1e);
$display("\n\n");
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h4, 15'h3124); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h5, 15'h6944); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h6, 15'h5182); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
fifo_info;
$display("FIFO should be full now");
// Following one is accepted with overrun
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
fifo_info;
release_rx_buffer_command;
fifo_info;
// Space just enough for the following frame.
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
fifo_info;
// Following accepted with overrun
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
fifo_info;
// read_overrun_info(0, 15);
release_rx_buffer_command;
release_rx_buffer_command;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
fifo_info;
// read_overrun_info(0, 15);
$display("\n\n");
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
clear_data_overrun_command;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
clear_data_overrun_command;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
// Read irq register
read_register(8'd3);
// Read irq register
read_register(8'd3);
#1000;
end
endtask
task test_full_fifo_ext;
begin
release_rx_buffer_command;
$display("\n\n");
read_receive_buffer;
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
read_receive_buffer;
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
read_receive_buffer;
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
fifo_info;
read_receive_buffer;
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
fifo_info;
// read_overrun_info(0, 10);
release_rx_buffer_command;
release_rx_buffer_command;
fifo_info;
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
fifo_info;
// read_overrun_info(0, 15);
$display("\n\n");
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
release_rx_buffer_command;
read_receive_buffer;
fifo_info;
end
endtask
/*
task initialize_fifo;
integer i;
begin
for (i=0; i<32; i=i+1)
begin
can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
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