can_top.syr

USB_I2C_MAC_FPGA_Code.rar

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: can_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : can_top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : can_top
Output Format                      : NGC
Target Device                      : xc2s300e-6-pq208

---- Source Options
Top Module Name                    : can_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : can_top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
Compiling source file "can_register_asyn.v"
Module <can_register_asyn> compiled
Compiling source file "can_register.v"
Module <can_register> compiled
Compiling source file "can_registers.v"
Compiling include file "can_defines.v"
Module <can_registers> compiled
Compiling source file "can_btl.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_btl> compiled
Compiling source file "can_crc.v"
Module <can_crc> compiled
Compiling source file "can_acf.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_acf> compiled
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_fifo> compiled
Compiling source file "can_ibo.v"
Module <can_ibo> compiled
Compiling source file "can_bsp.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_bsp> compiled
Compiling source file "can_top.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_top> compiled
No errors in compilation
Analysis of file <can_top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <can_top>.
WARNING:Xst:916 - can_top.v line 649: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 651: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 714: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 728: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 729: Delay is ignored for synthesis.
Module <can_top> is correct for synthesis.
 
Analyzing module <can_registers>.
WARNING:Xst:916 - can_registers.v line 443: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 444: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 445: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 446: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 447: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_registers> is correct for synthesis.
 
Analyzing module <can_register_asyn_syn>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn> is correct for synthesis.
 
Analyzing module <can_register_asyn>.
WARNING:Xst:916 - can_register_asyn.v line 101: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn.v line 103: Delay is ignored for synthesis.
Module <can_register_asyn> is correct for synthesis.
 
Analyzing module <can_register_asyn_1>.
WARNING:Xst:916 - can_register_asyn.v line 101: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn.v line 103: Delay is ignored for synthesis.
Module <can_register_asyn_1> is correct for synthesis.
 
Analyzing module <can_register_asyn_syn_1>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn_1> is correct for synthesis.
 
Analyzing module <can_register_asyn_syn_2>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn_2> is correct for synthesis.
 
Analyzing module <can_register>.
WARNING:Xst:916 - can_register.v line 98: Delay is ignored for synthesis.
Module <can_register> is correct for synthesis.
 
Analyzing module <can_register_asyn_2>.
WARNING:Xst:916 - can_register_asyn.v line 101: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn.v line 103: Delay is ignored for synthesis.
Module <can_register_asyn_2> is correct for synthesis.
 
Analyzing module <can_register_1>.
WARNING:Xst:916 - can_register.v line 98: Delay is ignored for synthesis.
Module <can_register_1> is correct for synthesis.
 
Analyzing module <can_register_2>.
WARNING:Xst:916 - can_register.v line 98: Delay is ignored for synthesis.
Module <can_register_2> is correct for synthesis.
 
Analyzing module <can_btl>.
WARNING:Xst:916 - can_btl.v line 205: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 207: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 216: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 218: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 237: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_btl> is correct for synthesis.
 
Analyzing module <can_bsp>.
WARNING:Xst:916 - can_bsp.v line 641: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 643: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 653: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 655: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 665: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
can_bsp.v line 1285: Found Parallel Case directive in module <can_bsp>.
can_bsp.v line 1296: Found Parallel Case directive in module <can_bsp>.
can_bsp.v line 1306: Found Parallel Case directive in module <can_bsp>.
INFO:Xst:1433 - Contents of array <tmp_fifo> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <r_calculated_crc> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <extended_chain_std> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <r_calculated_crc> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <basic_chain> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Module <can_bsp> is correct for synthesis.
 
Analyzing module <can_crc>.
WARNING:Xst:916 - can_crc.v line 96: Delay is ignored for synthesis.
WARNING:Xst:916 - can_crc.v line 100: Delay is ignored for synthesis.
WARNING:Xst:916 - can_crc.v line 102: Delay is ignored for synthesis.
Module <can_crc> is correct for synthesis.
 
Analyzing module <can_acf>.
WARNING:Xst:916 - can_acf.v line 346: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 348: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 353: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 355: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 359: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_acf> is correct for synthesis.
 
Analyzing module <can_fifo>.
WARNING:Xst:916 - can_fifo.v line 182: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 184: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 196: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 206: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_fifo> is correct for synthesis.
 
Analyzing module <RAMB4_S8_S8>.
Analyzing module <RAMB4_S4_S4>.
Analyzing module <RAMB4_S1_S1>.
Analyzing module <can_ibo>.
Module <can_ibo> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <can_ibo>.
    Related source file is can_ibo.v.
Unit <can_ibo> synthesized.


Synthesizing Unit <can_fifo>.
    Related source file is can_fifo.v.
WARNING:Xst:647 - Input <addr<7:6>> is never used.
WARNING:Xst:647 - Input <fifo_selected> is never used.
    Found 7-bit updown counter for signal <info_cnt>.
    Found 6-bit subtractor for signal <$n0019>.
    Found 7-bit addsub for signal <$n0020>.
    Found 7-bit subtractor for signal <$n0030> created at line 271.
    Found 6-bit adder for signal <$n0032> created at line 231.
    Found 1-bit xor2 for signal <$n0056> created at line 285.
    Found 7-bit register for signal <fifo_cnt>.
    Found 1-bit register for signal <latch_overrun>.
    Found 4-bit up counter for signal <len_cnt>.