can_fifo.syr

USB_I2C_MAC_FPGA_Code.rar

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: can_fifo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : can_fifo.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : can_fifo
Output Format                      : NGC
Target Device                      : xc2s300e-6-pq208

---- Source Options
Top Module Name                    : can_fifo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : can_fifo.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
Module <can_fifo> compiled
No errors in compilation
Analysis of file <can_fifo.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <can_fifo>.
WARNING:Xst:916 - can_fifo.v line 182: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 184: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 196: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 206: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_fifo> is correct for synthesis.
 
Analyzing module <RAMB4_S8_S8>.
Analyzing module <RAMB4_S4_S4>.
Analyzing module <RAMB4_S1_S1>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <can_fifo>.
    Related source file is can_fifo.v.
WARNING:Xst:647 - Input <addr<7:6>> is never used.
WARNING:Xst:647 - Input <fifo_selected> is never used.
    Found 7-bit updown counter for signal <info_cnt>.
    Found 6-bit subtractor for signal <$n0019>.
    Found 7-bit addsub for signal <$n0020>.
    Found 7-bit subtractor for signal <$n0030> created at line 271.
    Found 6-bit adder for signal <$n0032> created at line 231.
    Found 1-bit xor2 for signal <$n0056> created at line 285.
    Found 7-bit register for signal <fifo_cnt>.
    Found 1-bit register for signal <latch_overrun>.
    Found 4-bit up counter for signal <len_cnt>.
    Found 6-bit up counter for signal <rd_info_pointer>.
    Found 6-bit register for signal <rd_pointer>.
    Found 6-bit adder for signal <read_address>.
    Found 6-bit up counter for signal <wr_info_pointer>.
    Found 6-bit up counter for signal <wr_pointer>.
    Found 1-bit register for signal <wr_q>.
    Found 7 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   5 Counter(s).
	inferred  15 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   7 Multiplexer(s).
Unit <can_fifo> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 4
  1-bit register                   : 2
  6-bit register                   : 1
  7-bit register                   : 1
# Counters                         : 5
  4-bit up counter                 : 1
  6-bit up counter                 : 3
  7-bit updown counter             : 1
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 5
  6-bit adder                      : 2
  6-bit subtractor                 : 1
  7-bit addsub                     : 1
  7-bit subtractor                 : 1
# Xors                             : 1
  1-bit xor2                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <can_fifo> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block can_fifo, actual ratio is 2.