📄 l2_fponcmos.c
字号:
reg_data[0] = 0x41;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //bypass blm
reg_addr[0] = 0x0e;
reg_data[0] = 0x19;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x0f;
reg_data[0] = 0x47;//0x40; //jhyu@0722 test
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x13;
reg_data[0] = 0xc2; //James@20040602 mark 0xc0;//00;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x14;
reg_data[0] = 0xc6; //jhyu@line exposure
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x15;
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); // Use HREF
reg_addr[0] = 0x33; //jhyu@0722 test
reg_data[0] = 0x3c;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //hrd-reset and sa1-SF current
reg_addr[0] = 0x34; //jhyu@0722 test
reg_data[0] = 0x0c;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //hrd-reset and sa1-SF current
reg_addr[0] = 0x35;
reg_data[0] = 0x90;//60;//90;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x3c;
reg_data[0] = 0x41;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x38;
reg_data[0] = 0x52;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Black Level
#endif
////////////////////////////////////////////////////////////////////////////////
}
#endif
//-------------------Davis:patch_2005/Jun/07 begin
#ifdef OV3620
void L3_OVI2C_Write(UCHAR RegAddr, UCHAR RegData)
{
UCHAR reg_addr[6], reg_data[6];
reg_addr[0] = RegAddr;
reg_data[0] = RegData;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
}
void L3_CMOSIniPad28(void)
{
XBYTE[0x2007] = 0x00; //Set Output enable
XBYTE[0x2008] = 0x00;
XBYTE[0x2009] = 0x02; //Set Clk2x Output
XBYTE[0x200a] = 0x00; //Set SWTGole
XBYTE[0x200b] = 0x00;
}
void L3_CMOSIniClk28(void)
{
XBYTE[0x2080] = 0x00; //Disable TG PLL
XBYTE[0x2A80] = 0x00; //Disable HP, let Clk2x Change immediate
XBYTE[0x2A81] = 0x01; //Set Clk1xDiv
XBYTE[0x2A82] = 0x01; //Set Clk2xDiv
XBYTE[0x2019] = XBYTE[0x2019] & 0xBF; //Select input clk1x from External, clk2x from Internal
XBYTE[0x2A80] = 0x02; //Disable HP, let Clk2x Change sync witd Vd
}
void L3_CMOSIniPhase28(void) //Adjust this part to get better Image quality
{
XBYTE[0x2A83] = 0x00; //Clk1x Out delay
XBYTE[0x2023] = 0x00; //Clk1x Input delay
XBYTE[0x2022] = 0x00; //Clk2x Input delay
}
void L3_CMOSIniParameter28(void)
{
XBYTE[0x2AB0] = 0x01; //Reset Sensor interface
XBYTE[0x2AB0] = 0x00;
XBYTE[0x2A00] = 0x02; //Inverise Vsync input polarity
XBYTE[0x2A15] = 0x05; //Vfall
XBYTE[0x2A17] = 0x06; //Vrise
XBYTE[0x2A10] = 0x00; //V reshape enable
XBYTE[0x2A20] = 0x8;//0x48; //Set Hoffset //liumr modify
XBYTE[0x2A21] = 0x01;
XBYTE[0x2A22] = 0x06; //Set Voffset
XBYTE[0x2A23] = 0x00;
XBYTE[0x2A26] = 0x00; //Set Vsize
XBYTE[0x2A27] = 0x06;
XBYTE[0x2A24] = 0x00; //Set Hsize
XBYTE[0x2A25] = 0x08;
XBYTE[0x2A30] = 0xea; //Set Hoffsetm
XBYTE[0x2A31] = 0x01;
XBYTE[0x2A32] = 0x10; //Set Hsizem
XBYTE[0x2A33] = 0x04;
XBYTE[0x2A34] = 0x03; //Set Voffsetm
XBYTE[0x2A35] = 0x00;
XBYTE[0x2A36] = 0x0D; //Set Vsizem
XBYTE[0x2A37] = 0x03;
XBYTE[0x2A41] = 0x00; //Set LineTotal
XBYTE[0x2A42] = 0x06;
XBYTE[0x2A50] = 0x0C; //Set FrameTotalm
XBYTE[0x2A51] = 0x03;
XBYTE[0x203c] = XBYTE[0x203c] | 0x03; //Set GPIO 32 as FREX and GPIO 33 as EXPSTB
L2_Wait(200);
XBYTE[0X2900]= 0x60; // Set sensor slave address
XBYTE[0x2904]= 0x04; //Set to SSC Frequency
L3_OVI2C_Write(0x12,0x80);
L2_Wait(1);
L3_OVI2C_Write(0x12,0x40); // XGA MODE
L3_OVI2C_Write(0x01,0x80); // BLUE //liumr modify
L3_OVI2C_Write(0x02,0x80); // RED
L3_OVI2C_Write(0x03,0x4c); // COMA
L3_OVI2C_Write(0x4,0x8);
L3_OVI2C_Write(0x09,0x08); // COMC
L3_OVI2C_Write(0x0c,0x8); // COMG
L3_OVI2C_Write(0x0d,0x81); // COMG
L3_OVI2C_Write(0x0e,0x00); // COMG
L3_OVI2C_Write(0x0F,0x42); // COMG//???? //0x43
L3_OVI2C_Write(0x49,0x89); // Negative Voltage
L3_OVI2C_Write(0x10,0x40); // COMG
L3_OVI2C_Write(0x11,0x00); // CLKRC
L3_OVI2C_Write(0x13,0xc0); // CLKRC
L3_OVI2C_Write(0x14,0xc6);
L3_OVI2C_Write(0x15,0x80);
L3_OVI2C_Write(0x19,0x0); // VSTRT
L3_OVI2C_Write(0x33,0x19);
L3_OVI2C_Write(0x34,0x58/*0x1B*/); // VGAP
L3_OVI2C_Write(0x35,0x4c); // ARBLM; Set VrLo=0.3v
L3_OVI2C_Write(0x36,0x00);
L3_OVI2C_Write(0x37,0x04); // ADC
L3_OVI2C_Write(0x38,0x52); // ACOM
L3_OVI2C_Write(0x3A,0x00);
L3_OVI2C_Write(0x3b,0x18);
L3_OVI2C_Write(0x3c,0x1f);
L3_OVI2C_Write(0x3d,0x00);
L3_OVI2C_Write(0x3e,0x00);
L3_OVI2C_Write(0x3F,0); //??????// REG3F
L3_OVI2C_Write(0x40,253); //B channel
L3_OVI2C_Write(0x41,253); //R channel
L3_OVI2C_Write(0x42,244); //Gb channel
L3_OVI2C_Write(0x43,241); //Gr channel
L3_OVI2C_Write(0x44,0x00);
L3_OVI2C_Write(0x45,0x80);
L3_OVI2C_Write(0x48,0xc0); // RSVD48; Cancel Image Lag
L3_OVI2C_Write(0x4b,0x80);
L3_OVI2C_Write(0x4D,0xC4); // RSVD4D
L3_OVI2C_Write(0x1a,0xc0);
L3_OVI2C_Write(0x4,0x8);
L3_OVI2C_Write(0x1b,0x1);
}
#endif
//-------------------Davis:patch_2005/Jun/07 end
#ifdef MCM20027 // Motorola 1.3M CMOS Sensor
void L3_CMOSIniPad02(void) USING_0
{
XBYTE[0x2007] = 0x00; //Set Output enable
XBYTE[0x2008] = 0x00;
XBYTE[0x2009] = 0x02; //Set Clk2x Output
XBYTE[0x200a] = 0x00; //Set SWTGole
XBYTE[0x200b] = 0x00;
}
void L3_CMOSIniClk02(void) USING_0
{
XBYTE[0x2080] = 0x00; //Disable TG PLL
XBYTE[0x2A80] = 0x00; //Disable HP, let Clk2x Change immediate
XBYTE[0x2A81] = 0x00; //Set Clk1xDiv
XBYTE[0x2A82] = 0x06; //Set Clk2xDiv, the Pixclk will be 12Mhz
XBYTE[0x2019] = XBYTE[0x2019] & 0x3F; //Select input clk1x , clk2x from PAD
XBYTE[0x2A80] = 0x02; //Disable HP, let Clk2x Change sync witd Vd
}
void L3_CMOSIniPhase02(void) //Adjust this part to get better Image quality
{
XBYTE[0x2A83] = 0x00; //Clk1x Out delay
//Joe@2003.3.17 19:46 modify begin
//XBYTE[0x2023] = 0x01; //Clk1x Input delay
XBYTE[0x2023] = 0x02; //Clk1x Input delay
//Joe@2003.3.17 19:46 modify end
XBYTE[0x2022] = 0x00; //Clk2x Input delay
}
void L3_CMOSIniParameter02(void) USING_0
{
UCHAR reg_addr[7], reg_data[7];
XBYTE[0x2AB0] = 0x01; //Reset Sensor interface
XBYTE[0x2AB0] = 0x00;
XBYTE[0x2A00] = 0x03; //Inverise Vsync , Hsync input polarity
XBYTE[0x2A11] = 0x00; //Hfall (Low)
XBYTE[0x2A13] = 0x02; //Hrise (Low)
XBYTE[0x2A10] = 0x01; //Hreshape ensble
XBYTE[0x2A20] = 0x31; //Set Hoffset
XBYTE[0x2A21] = 0x00;
XBYTE[0x2A22] = 0x03; //Set Voffset
XBYTE[0x2A23] = 0x00;
XBYTE[0x2A24] = 0x00; //Set Hsize = 1280
XBYTE[0x2A25] = 0x05;
XBYTE[0x2A26] = 0x00; //Set Vsize = 1024
XBYTE[0x2A27] = 0x04;
XBYTE[0x2A30] = 0x31; //Set Hoffsetm
XBYTE[0x2A31] = 0x00;
XBYTE[0x2A32] = 0x80; //Set Hsizem
XBYTE[0x2A33] = 0x02;
XBYTE[0x2A34] = 0x0C; //Set Voffsetm
XBYTE[0x2A35] = 0x00;
XBYTE[0x2A36] = 0xED; //Set Vsizem
XBYTE[0x2A37] = 0x01;
XBYTE[0x2A41] = 0x3B; //Set LineTotal //patch4.3@jhyu@0612
XBYTE[0x2A42] = 0x03;
XBYTE[0x2A50] = 0x26; //Set FrameTotalm
XBYTE[0x2A51] = 0x02;
//Use SSC to initializes CMOS sensor register/////////////////////////////////// // Ov9620 1.3M CMOS Sensor
XBYTE[0X2900] = 0x66; //Set sensor slave address
XBYTE[0x2904] = 0x03; //Set to SSC Frequency
//Initial Setting //////////////////////////////////////////////////////////////
reg_addr[0] = 0x0E; //Reset CMOS sensor
reg_data[0] = 0x1F;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x0E;
reg_data[0] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
//Joe@2003.3.18 9:28 add for purple screen after snap begin
reg_addr[0] = 0x0C; //Reset CMOS sensor
reg_data[0] = 0x08;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
//Joe@2003.3.18 9:28 add for purple screen after snap end
reg_addr[0] = 0x0A; //ADC nvr
reg_data[0] = 0x76;
reg_addr[1] = 0x0B; //ADC pvr
reg_data[1] = 0x80;
reg_addr[2] = 0x40; //Continous HCLK,VCLK
reg_data[2] = 0x3E;
reg_addr[3] = 0x5F; //shr = 32
reg_data[3] = 0x20;
reg_addr[4] = 0x60; //shs = 32
reg_data[4] = 0x20;
reg_addr[5] = 0x46; //WOI ROW pointer (LSB)
reg_data[5] = 0x0E;
reg_addr[6] = 0x4A; //WOI Column pointer (LSB)
reg_data[6] = 0x04;
L2_WriteSSC(reg_addr, reg_data, 0x07, 0x02);
reg_addr[0] = 0x41;
reg_data[0] = 0x15;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x50; //Virtual frame Row Depth MSB
reg_data[0] = 0x02;
reg_addr[1] = 0x51; //Virtual frame Row Depth LSB
reg_data[1] = 0x26;
reg_addr[2] = 0x52; //Virtual frame Column Depth MSB
reg_data[2] = 0x02;
reg_addr[3] = 0x53; //Virtual frame Column Depth LSB
reg_data[3] = 0xE8;
L2_WriteSSC(reg_addr, reg_data, 0x04, 0x02);
//patch4.3@jhyu@0606
reg_addr[0] = 0x47; //Integration Time
reg_data[0] = 0x04;
reg_addr[1] = 0x48; //Integration Time
reg_data[1] = 0x04;
L2_WriteSSC(reg_addr, reg_data, 0x02, 0x02);
//patch4.3@jhyu@0612
reg_addr[0] = 0x21;
reg_data[0] = 0x0e;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x4E; //Integration Time
reg_data[0] = 0x02;
reg_addr[1] = 0x4F; //Integration Time
reg_data[1] = 0x25;
L2_WriteSSC(reg_addr, reg_data, 0x02, 0x02);
////////////////////////////////////////////////////////////////////////////////
}
#endif
#ifdef ICM105 // IC-media VGA CMOS Sensor
void L3_CMOSIniPad10(void) USING_0
{
XBYTE[0x2007] = 0x00; //Set Output enable
XBYTE[0x2008] = 0x00;
XBYTE[0x2009] = 0x02; //Set Clk2x Output
XBYTE[0x200a] = 0x00; //Set SWTGole
XBYTE[0x200b] = 0x00;
XBYTE[0x2019] = XBYTE[0x2019] & 0xBF; //Set Clk1x from PAD
}
void L3_CMOSIniClk10(void) USING_0
{
UCHAR temp;
XBYTE[0x2080] = 0x00; //Disable TG PLL
XBYTE[0x2A80] = 0x00; //Disable HP, let Clk2x Change immediate
XBYTE[0x2A81] = 0x01; //Set Clk1xDiv
XBYTE[0x2A82] = 0x03; //Set Clk2xDiv, the Pixclk will be 12Mhz
temp = XBYTE[0x2019];
XBYTE[0x2019] = temp | 0xC0; //Select input clk1x, clk2x from PAD
XBYTE[0x2A80] = 0x02; //Disable HP, let Clk2x Change sync witd Vd
}
void L3_CMOSIniPhase10(void) USING_0 //Adjust this part to get better Image quality
{
XBYTE[0x2A83] = 0x00; //Clk1x Out delay
XBYTE[0x2023] = 0x00; //Clk1x Input delay
XBYTE[0x2022] = 0x00; //Clk2x Input delay
}
void L3_CMOSIniParameter10(void) USING_0
{
UCHAR reg_addr[8], reg_data[8];
XBYTE[0x2AB0] = 0x01; //Reset Sensor interface
XBYTE[0x2AB0] = 0x00;
XBYTE[0x2A00] = 0x00; //Inverise Vsync input polarity
XBYTE[0x2A20] = 0x55; //Set Hoffset
XBYTE[0x2A21] = 0x00;
XBYTE[0x2A22] = 0x05; //Set Voffset
XBYTE[0x2A23] = 0x00;
XBYTE[0x2A24] = 0x80; //Set Hsize
XBYTE[0x2A25] = 0x02;
XBYTE[0x2A26] = 0xF0; //Set Vsize
XBYTE[0x2A27] = 0x01;
XBYTE[0x2A30] = 0xA8; //Set Hoffsetm
XBYTE[0x2A31] = 0x00;
XBYTE[0x2A32] = 0xE0; //Set Hsizem
XBYTE[0x2A33] = 0x01;
XBYTE[0x2A34] = 0x06; //Set Voffsetm
XBYTE[0x2A35] = 0x00;
XBYTE[0x2A36] = 0xE0; //Set Vsizem
XBYTE[0x2A37] = 0x01;
XBYTE[0x2A41] = 0x5A; //Set LineTotal
XBYTE[0x2A42] = 0x03;
XBYTE[0x2A50] = 0x07; //Set FrameTotalm
XBYTE[0x2A51] = 0x02;
//Use SSC to initializes CMOS sensor register/////////////////////////////////// // Ov9620 1.3M CMOS Sensor
XBYTE[0X2900] = 0x42; //Set sensor slave address
XBYTE[0x2904] = 0x03; //Set to SSC Frequency
//Set Wave table //////////////////////////////////////////////////////////////
reg_addr[0] = 0x01;
reg_data[0] = 0x30;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Burst SSC Write
//Vector 0
reg_addr[0] = 0x03;
reg_data[0] = 0x00;
reg_addr[1] = 0x04;
reg_data[1] = 0x03;
reg_addr[2] = 0x05;
reg_data[2] = 0x00;
reg_addr[3] = 0x06;
reg_data[3] = 0x01;
reg_addr[4] = 0x08;
reg_data[4] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x05, 0x02); //Set Burst SSC Write
//Vector 1
reg_addr[0] = 0x03;
reg_data[0] = 0x01;
reg_addr[1] = 0x04;
reg_data[1] = 0x21;
reg_addr[2] = 0x05;
reg_data[2] = 0x80;
reg_addr[3] = 0x06;
reg_data[3] = 0x01;
reg_addr[4] = 0x08;
reg_data[4] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x05, 0x02); //Set Burst SSC Write
//Vector 2
reg_addr[0] = 0x03;
reg_data[0] = 0x02;
reg_addr[1] = 0x04;
reg_data[1] = 0x25;
reg_addr[2] = 0x05;
reg_data[2] = 0x00;
reg_addr[3] = 0x06;
reg_data[3] = 0x01;
reg_addr[4] = 0x08;
reg_data[4] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x05, 0x02); //Set Burst SSC Write
//Vector 3
reg_addr[0] = 0x03;
reg_data[0] = 0x03;
reg_addr[1] = 0x04;
reg_data[1] = 0x35;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -