📄 l2_fponcmos.c
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for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x13; //Set COMI
reg_data[0] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x01; //Set blue Gain
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x02; //Set Red Gain
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x03; //Blue, Red bow bits Gain
reg_data[0] = 0x40;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x2A;
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x2B;
reg_data[0] = 00;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
//patch4.3@jhyu@0606
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x14;
reg_data[0] = 0x46;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x0E;
reg_data[0] = 00;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x33;
reg_data[0] = 0x28;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x35;
reg_data[0] = 0x90;//patch4.5@andrew@OV13_A Blooming //patch4.4@jhyu@reduce_blooming
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x36;
reg_data[0] = 0x17;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
//patch4.3@jhyu@0606
reg_addr[0] = 0x17;
reg_data[0] = 0x11;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
reg_addr[0] = 0x1a;
reg_data[0] = 0x7b;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
//patch4.5@andrew@OV13_A // AD range
reg_addr[0] = 0x37;
reg_data[0] = 0x05;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
#if 1
//for ov 9630
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x33;
reg_data[0] = 0xdf;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x35;
reg_data[0] = 0x64;//patch4.5@andrew@OV13_A Blooming //patch4.4@jhyu@reduce_blooming
L2_WriteSSC(reg_addr, reg_data, 1, 0);
for (i=0; i<40;i++) //Delay
for (j=0; j<255; j++);
reg_addr[0] = 0x36;
reg_data[0] = 0x37;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
reg_addr[0] = 0x14;
reg_data[0] = 0x40;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
reg_addr[0] = 0x0f;
reg_data[0] = 0x43;
L2_WriteSSC(reg_addr, reg_data, 1, 0);
#endif
////////////////////////////////////////////////////////////////////////////////
}
#endif
#ifdef OV2610 // Ov2610 2.0M CMOS Sensor
void L3_CMOSIniPad17(void)
{
XBYTE[0x2007] = 0x00; //Set Output enable
XBYTE[0x2008] = 0x00;
XBYTE[0x2009] = 0x02; //Set Clk2x Output
XBYTE[0x200a] = 0x00; //Set SWTGole
XBYTE[0x200b] = 0x00;
}
void L3_CMOSIniClk17(void)
{
XBYTE[0x2080] = 0x00; //Disable TG PLL
XBYTE[0x2A80] = 0x00; //Disable HP, let Clk2x Change immediate
XBYTE[0x2A81] = 0x01; //Set Clk1xDiv
XBYTE[0x2A82] = 0x03; //Set Clk2xDiv
//Joe@2003.2.27 13:55 modify begin
//XBYTE[0x2019] = XBYTE[0x2019] | 0xC0; //Select input clk1x, clk2x from Internal
XBYTE[0x2019] = XBYTE[0x2019] | 0x80; //Select input clk2x from Internal
XBYTE[0x2019] = XBYTE[0x2019] & 0xbf; //Select input clk1x from External
//Joe@2003.2.27 13:55 modify end
XBYTE[0x2A80] = 0x02; //Disable HP, let Clk2x Change sync witd Vd
}
void L3_CMOSIniPhase17(void) //Adjust this part to get better Image quality
{
XBYTE[0x2A83] = 0x00; //Clk1x Out delay
XBYTE[0x2023] = 0x02;//10; //Clk1x Input delay
XBYTE[0x2022] = 0x00; //Clk2x Input delay
}
void L3_CMOSIniParameter17(void)
{
UCHAR reg_addr[6], reg_data[6];
UCHAR i,j;
XBYTE[0X2100] = 0x02;//ccfan
XBYTE[0X2023] = 0x02;//ccfan
XBYTE[0x2AB0] = 0x01; //Reset Sensor interface
XBYTE[0x2AB0] = 0x00;
XBYTE[0x2A00] = 0x02; //Inverise Vsync input polarity
XBYTE[0x2A15] = 0x05;//04;//ccfan //Vfall
XBYTE[0x2A17] = 0x06;//00;//ccfan //Vrise
XBYTE[0x2A10] = 0x00;//02;//ccfan //V reshape enable
XBYTE[0x2A20] = 0x48;//39;//ccfan //Set Hoffset
XBYTE[0x2A21] = 0x01;
XBYTE[0x2A22] = 0x0d; //Set Voffset
XBYTE[0x2A23] = 0x00;
XBYTE[0x2A26] = 0xb0;//be;//ccfan //Set Vsize
XBYTE[0x2A27] = 0x04;
XBYTE[0x2A24] = 0x52;//50;//ccfan //Set Hsize
XBYTE[0x2A25] = 0x06;
XBYTE[0x2A30] = 0x79;//77;//ccfan //Set Hoffsetm
XBYTE[0x2A31] = 0x00;
XBYTE[0x2A32] = 0x80; //Set Hsizem
XBYTE[0x2A33] = 0x02;
XBYTE[0x2A34] = 0x09;//08;//ccfan //Set Voffsetm
XBYTE[0x2A35] = 0x00;
XBYTE[0x2A36] = 0xED; //Set Vsizem
XBYTE[0x2A37] = 0x01;
XBYTE[0x2A41] = 0xCE; //Set LineTotal
XBYTE[0x2A42] = 0x03;
XBYTE[0x2A50] = 0x68; //Set FrameTotalm
XBYTE[0x2A51] = 0x02;
//L2_Wait(200);
//Use SSC to initializes CMOS sensor register/////////////////////////////////// // Ov9620 1.3M CMOS Sensor
XBYTE[0X2900]= 0x60; // Set sensor slave address
XBYTE[0x2904]= 0x04; //Set to SSC Frequency
reg_addr[0] = 0x12; //Rst Sensor
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x12; //Set VGA Mode
reg_data[0] = 0x60;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x0e;
reg_data[0] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x13;
reg_data[0] = 0x00;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x14;
reg_data[0] = 0x46;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x01; //Set blue Gain
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x02; //Set Red Gain
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x03; //Blue, Red bow bits Gain
reg_data[0] = 0x40;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x35;
reg_data[0] = 0x90;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x36;
reg_data[0] = 0x37;//17;//37;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x33;
reg_data[0] = 0x0c;//54;//0a;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x1a; //Set VEND
reg_data[0] = 0x98;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x09;
reg_data[0] = 0x01;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x0d;
reg_data[0] = 0x40;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
////////////////////////////////////////////////////////////////////////////////
}
#endif
#ifdef OV3610 // Ov2610 2.0M CMOS Sensor
void L3_CMOSIniPad20(void)
{
XBYTE[0x2007] = 0x00; //Set Output enable
XBYTE[0x2008] = 0x00;
XBYTE[0x2009] = 0x02; //Set Clk2x Output
XBYTE[0x200a] = 0x00; //Set SWTGole
XBYTE[0x200b] = 0x00;
}
void L3_CMOSIniClk20(void)
{
XBYTE[0x2080] = 0x00; //Disable TG PLL
XBYTE[0x2A80] = 0x00; //Disable HP, let Clk2x Change immediate
XBYTE[0x2A81] = 0x01; //Set Clk1xDiv
XBYTE[0x2A82] = 0x01; //Set Clk2xDiv
XBYTE[0x2019] = XBYTE[0x2019] & 0xBF; //Select input clk1x from External, clk2x from Internal
XBYTE[0x2A80] = 0x02; //Disable HP, let Clk2x Change sync witd Vd
}
void L3_CMOSIniPhase20(void) //Adjust this part to get better Image quality
{
XBYTE[0x2A83] = 0x00; //Clk1x Out delay
XBYTE[0x2023] = 0x00; //Clk1x Input delay
XBYTE[0x2022] = 0x00; //Clk2x Input delay
}
void L3_CMOSIniParameter20(void) //patch5.2.1@jhyu@OV3610
{
UCHAR reg_addr[6], reg_data[6];
USHORT i;//,j;
XBYTE[0x2AB0] = 0x01; //Reset Sensor interface
XBYTE[0x2AB0] = 0x00;
XBYTE[0x2A00] = 0x02; //Inverise Vsync input polarity
XBYTE[0x2A15] = 0x05; //Vfall
XBYTE[0x2A17] = 0x06; //Vrise
XBYTE[0x2A10] = 0x00; //V reshape enable
XBYTE[0x2A20] = 0x10; //Set Hoffset
XBYTE[0x2A21] = 0x01;
XBYTE[0x2A22] = 0x03; //Set Voffset
XBYTE[0x2A23] = 0x00;
XBYTE[0x2A26] = 0x00; //Set Vsize
XBYTE[0x2A27] = 0x06;
XBYTE[0x2A24] = 0x00; //Set Hsize
XBYTE[0x2A25] = 0x08;
XBYTE[0x2A30] = 0x18;//0xea; Jane@050308 modified //Set Hoffsetm //jhyu@0304
XBYTE[0x2A31] = 0x02; //0x01
XBYTE[0x2A32] = 0x10; //Set Hsizem
XBYTE[0x2A33] = 0x04;
XBYTE[0x2A34] = 0x02; //Set Voffsetm
XBYTE[0x2A35] = 0x00;
XBYTE[0x2A36] = 0x0D; //Set Vsizem
XBYTE[0x2A37] = 0x03;
XBYTE[0x2A41] = 0x00; //Set LineTotal
XBYTE[0x2A42] = 0x06;
XBYTE[0x2A50] = 0x0C; //Set FrameTotalm
XBYTE[0x2A51] = 0x03;
XBYTE[0x203c] = XBYTE[0x203c] | 0x03; //Set GPIO 32 as FREX and GPIO 33 as EXPSTB
L2_Wait(200);
//Use SSC to initializes CMOS sensor register/////////////////////////////////// // Ov9620 1.3M CMOS Sensor
XBYTE[0X2900]= 0x60; // Set sensor slave address
XBYTE[0x2904]= 0x04; //Set to SSC Frequency
reg_addr[0] = 0x12; //Rst Sensor
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
for(i=0;i<2000;i++);
reg_addr[0] = 0x12; //Rst Sensor
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
//for(i=0;i<1000;i++);
#if 0
reg_addr[0] = 0x12;
reg_data[0] = 0x40; //jhyu@OV3610 MP
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x03;
reg_data[0] = 0x44; //jhyu@OV3610 MP
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x17;
reg_data[0] = 0x16; //jhyu@OV3610 MP
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
// reg_addr[0] = 0x1a;
// reg_data[0] = 0x6C;
// L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
// reg_addr[0] = 0x09;
// reg_data[0] = 0x01;//00;
// L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x0c;
reg_data[0] = 0x38;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //remove h-line
reg_addr[0] = 0x0d;
reg_data[0] = 0x40;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //bypass blm
// reg_addr[0] = 0x0e;
// reg_data[0] = 0x05;
// L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //disable analog average@QXGA
reg_addr[0] = 0x0f;
reg_data[0] = 0x40;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x13;
reg_data[0] = 0xc0;//00;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x14;
reg_data[0] = 0xc6;//46;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Set Seq SSC Write
reg_addr[0] = 0x15;
reg_data[0] = 0x80;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); // Use HREF
// reg_addr[0] = 0x16;
// reg_data[0] = 0x00;
// L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
// reg_addr[0] = 0x32;
// reg_data[0] = 0x36;
// L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //correct h-window
reg_addr[0] = 0x33;
reg_data[0] = 0x3d;//3f;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //Min Ibit
reg_addr[0] = 0x34;
reg_data[0] = 0x8c;//93;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //hrd-reset and sa1-SF current
reg_addr[0] = 0x35;
reg_data[0] = 0x90;//60;//90;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x36;
reg_data[0] = 0x37;//17;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
/*
reg_addr[0] = 0x37;
reg_data[0] = 0x04;//08;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x38;
reg_data[0] = 0x13;//12;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
*/
//0418
reg_addr[0] = 0x3c;
reg_data[0] = 0x41;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
#else
reg_addr[0] = 0x12;
reg_data[0] = 0x40; //jhyu@OV3610 MP
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x11;
reg_data[0] = 0x81; //jhyu@line exposure
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x03;
reg_data[0] = 0x44; //jhyu@OV3610 MP
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x17;
reg_data[0] = 0x26; //0x16; //jhyu@OV3610 MP
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00);
reg_addr[0] = 0x0c;
reg_data[0] = 0x38;
L2_WriteSSC(reg_addr, reg_data, 0x01, 0x00); //remove h-line
reg_addr[0] = 0x0d;
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