📄 l2_cpu_irq.c
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/*++
Copyright (c) 2001 Sunplus Technology Co., Ltd.
Module Name:
L2_cpu.c
Abstract:
Module related to L2 CPU functions
Environment:
Keil C51 Compiler
Revision History:
11/12/2001 WZH created
--*/
//=============================================================================
//Header file
//=============================================================================
#include "general.h"
#include "L2.h"
//=============================================================================
//Symbol
//=============================================================================
//-----------------------------------------------------------------------------
//Constant
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//Variable
//-----------------------------------------------------------------------------
sfr RamPage = 0x9B;
sfr MemStretch = 0x8E;
//=============================================================================
//Program
//=============================================================================
//-----------------------------------------------------------------------------
//L2_InitCPU
//-----------------------------------------------------------------------------
/*
routine description:
cpu interface hardware initialization
arguments:
CamMode: camera operation mode
return value:
0x00 - success
others - error
*/
UCHAR L2_InitCPU(UCHAR CamMode) USING_0
{
//PRINT_L2("Enter \"L2_InitCPU\"\n");
if(CamMode > 6) return 0x01;
if(CamMode == 0)
{
MemStretch = 0x00; // memory stretch = 0
XBYTE[0x2C00] = 0x0F; // rampageen, rompageen, SRAM enable
XBYTE[0x2024] = 0x01; // CPU clock
//Joe@2003.3.14 20:56 modify begin
/*
if(L2K_CPUInternal == 1)
{
XBYTE[0x2C02] = L2K_P1OE; // P1 & P3 are always drive
XBYTE[0x2C03] = L2K_P3OE;
//P1 = 0xff;
P3 = 0xff;
}
else
{
XBYTE[0x2C02] = 0x00;
XBYTE[0x2C03] = 0x00;
}
if(L2K_CPUP1 == 1)
XBYTE[0x201A] = (XBYTE[0X201A] & 0x0f); // P1 is used for GPIO
else
XBYTE[0x201A] = (XBYTE[0X201A] | 0x10);
*/
UI_SetCPUPort();
//Joe@2003.3.14 20:56 modify end
RamPage = 0x00;
}
//PRINT_L2("Exit \"L2_InitCPU\"\n");
return L2K_SUCCESS;
}
//-----------------------------------------------------------------------------
//L2_DownloadROM
//-----------------------------------------------------------------------------
/*
routine description:
upload data from external ROM to 4K SRAM
arguments:
Addr: 4K SRAM write address
ROMAddr: external ROM read address
nByte: the number of byte to be transfer // maximum size is 4K bytes
return value:
0x00 - success
others - error
Note: cross page is not available to reduce the dummy coding time
*/
UCHAR L2_DownloadROM(USHORT SRAMAddr, ULONG ROMAddr, USHORT nByte) USING_0
{
USHORT srcend;
USHORT i, romaddrl;
UCHAR tmp0;
//PRINT_L2("Enter \"L2_DownloadROM\"(Addr=%x,ROMAddr=%lx,nByte=%x)\n",SRAMAddr,ROMAddr,(USHORT)nByte);
romaddrl = ROMAddr & 0x00007FFF ;
RamPage = ROMAddr & 0x000F8000 ;
srcend = nByte + 0x8000;
if((SRAMAddr & 0xF000)!=0) return 0x01;
XBYTE[0x2C12] = (SRAMAddr & 0x00FF);
XBYTE[0x2C13] = (SRAMAddr & 0x0F00) >> 8;
tmp0 = XBYTE[0x2C00];
XBYTE[0x2C00] = tmp0 & 0x1d;
XBYTE[0x2C11] = 0x06;
XBYTE[0x2C11] = 0x01;
XBYTE[0x2C00] = tmp0 | 0x02;
for(i=0x8000 ; i<srcend ; i++)
{
XBYTE[0x2C10] = XBYTE[romaddrl+i];
}
//PRINT_L2("romaddr=%x,RamPage=%x,SrcEnd=%x \n",romaddrl,(USHORT)RamPage,srcend);
//PRINT_L2("Exit \"L2_DownloadROM\"\n");
return L2K_SUCCESS;
}
//-----------------------------------------------------------------------------
//L2_SetIRQEn
//-----------------------------------------------------------------------------
/*
routine description:
Set IRQ enable bits
arguments:
bmUSBIRQEn:
[0x00]: 0: IRQID_00 enable bit unchanged 1: set IRQID_00 enable bit
[0x01]: 0: IRQID_01 enable bit unchanged 1: set IRQID_01 enable bit
[0x02]: 0: IRQID_02 enable bit unchanged 1: set IRQID_02 enable bit
[0x03]: 0: IRQID_03 enable bit unchanged 1: set IRQID_03 enable bit
[0x04]: 0: IRQID_04 enable bit unchanged 1: set IRQID_04 enable bit
[0x05]: 0: IRQID_05 enable bit unchanged 1: set IRQID_05 enable bit
[0x06]: 0: IRQID_06 enable bit unchanged 1: set IRQID_06 enable bit
[0x07]: 0: IRQID_07 enable bit unchanged 1: set IRQID_07 enable bit
[0x08]: 0: IRQID_08 enable bit unchanged 1: set IRQID_08 enable bit
[0x09]: 0: IRQID_09 enable bit unchanged 1: set IRQID_09 enable bit
[0x0e]: 0: IRQID_0e enable bit unchanged 1: set IRQID_0e enable bit
[0x0f]: 0: IRQID_0f enable bit unchanged 1: set IRQID_0f enable bit
[0x10]: 0: IRQID_10 enable bit unchanged 1: set IRQID_10 enable bit
[0x11]: 0: IRQID_11 enable bit unchanged 1: set IRQID_11 enable bit
[0x12]: 0: IRQID_12 enable bit unchanged 1: set IRQID_12 enable bit
[0x13]: 0: IRQID_13 enable bit unchanged 1: set IRQID_13 enable bit
[0x14]: 0: IRQID_14 enable bit unchanged 1: set IRQID_14 enable bit
[0x15]: 0: IRQID_15 enable bit unchanged 1: set IRQID_15 enable bit
bmGlobalIRQEn:
[0]: 0: IRQID_20 enable bit unchanged 1: set IRQID_20 enable bit
[1]: 0: IRQID_21 enable bit unchanged 1: set IRQID_21 enable bit
[2]: 0: IRQID_22 enable bit unchanged 1: set IRQID_22 enable bit
[3]: 0: IRQID_23 enable bit unchanged 1: set IRQID_23 enable bit
[4]: 0: IRQID_24 enable bit unchanged 1: set IRQID_24 enable bit
[5]: 0: IRQID_25 enable bit unchanged 1: set IRQID_25 enable bit
[6]: 0: IRQID_26 enable bit unchanged 1: set IRQID_26 enable bit
[7]: 0: IRQID_27 enable bit unchanged 1: set IRQID_27 enable bit
bmSDRAMIRQEn:
[0]: 0: IRQID_30 enable bit unchanged 1: set IRQID_30 enable bit
return value:
0x00 - success
others - error
*/
UCHAR L2_SetIRQEn(ULONG bmUSBIRQEn, UCHAR bmGlobalIRQEn, UCHAR bmSDRAMEn) USING_0
{
//PRINT_L2("Enter \"L2_SetIRQEn\"\n");
XBYTE[0x25D0] |= (UCHAR)bmUSBIRQEn;
XBYTE[0x25D1] |= (UCHAR)(bmUSBIRQEn>>8);
XBYTE[0x25D2] |= (UCHAR)(bmUSBIRQEn>>16);
XBYTE[0x20D0] |= bmGlobalIRQEn;
XBYTE[0x27D0] |= bmSDRAMIRQEn;
//PRINT_L2("Exit \"L2_SetIRQEn\"\n");
return L2K_SUCCESS;
}
//-----------------------------------------------------------------------------
//L2_ClearIRQEn
//-----------------------------------------------------------------------------
/*
routine description:
Clear IRQ enable bits
arguments:
bmUSBIRQEn:
[0x00]: 0: IRQID_00 enable bit unchanged 1: clear IRQID_00 enable bit
[0x01]: 0: IRQID_01 enable bit unchanged 1: clear IRQID_01 enable bit
[0x02]: 0: IRQID_02 enable bit unchanged 1: clear IRQID_02 enable bit
[0x03]: 0: IRQID_03 enable bit unchanged 1: clear IRQID_03 enable bit
[0x04]: 0: IRQID_04 enable bit unchanged 1: clear IRQID_04 enable bit
[0x05]: 0: IRQID_05 enable bit unchanged 1: clear IRQID_05 enable bit
[0x06]: 0: IRQID_06 enable bit unchanged 1: clear IRQID_06 enable bit
[0x07]: 0: IRQID_07 enable bit unchanged 1: clear IRQID_07 enable bit
[0x08]: 0: IRQID_08 enable bit unchanged 1: clear IRQID_08 enable bit
[0x09]: 0: IRQID_09 enable bit unchanged 1: clear IRQID_09 enable bit
[0x0e]: 0: IRQID_0e enable bit unchanged 1: clear IRQID_0e enable bit
[0x0f]: 0: IRQID_0f enable bit unchanged 1: clear IRQID_0f enable bit
[0x10]: 0: IRQID_10 enable bit unchanged 1: clear IRQID_10 enable bit
[0x11]: 0: IRQID_11 enable bit unchanged 1: clear IRQID_11 enable bit
[0x12]: 0: IRQID_12 enable bit unchanged 1: clear IRQID_12 enable bit
[0x13]: 0: IRQID_13 enable bit unchanged 1: clear IRQID_13 enable bit
[0x14]: 0: IRQID_14 enable bit unchanged 1: clear IRQID_14 enable bit
[0x15]: 0: IRQID_15 enable bit unchanged 1: clear IRQID_15 enable bit
bmGlobalIRQEn:
[0]: 0: IRQID_20 enable bit unchanged 1: clear IRQID_20 enable bit
[1]: 0: IRQID_21 enable bit unchanged 1: clear IRQID_21 enable bit
[2]: 0: IRQID_22 enable bit unchanged 1: clear IRQID_22 enable bit
[3]: 0: IRQID_23 enable bit unchanged 1: clear IRQID_23 enable bit
[4]: 0: IRQID_24 enable bit unchanged 1: clear IRQID_24 enable bit
[5]: 0: IRQID_25 enable bit unchanged 1: clear IRQID_25 enable bit
[6]: 0: IRQID_26 enable bit unchanged 1: clear IRQID_26 enable bit
[7]: 0: IRQID_27 enable bit unchanged 1: clear IRQID_27 enable bit
bmSDRAMIRQEn:
[0]: 0: IRQID_30 enable bit unchanged 1: clear IRQID_30 enable bit
return value:
0x00 - success
others - error
*/
UCHAR L2_ClearIRQEn(ULONG bmUSBIRQEn, UCHAR bmGlobalIRQEn, UCHAR bmSDRAMEn) USING_0
{
//PRINT_L2("Enter \"L2_ClearIRQEn\"\n");
XBYTE[0x25D0] &= ~((UCHAR)bmUSBIRQEn);
XBYTE[0x25D1] &= ~((UCHAR)(bmUSBIRQEn>>8));
XBYTE[0x25D2] &= ~((UCHAR)(bmUSBIRQEn>>16));
XBYTE[0x20D0] &= ~(bmGlobalIRQEn);
XBYTE[0x27D0] &= ~(bmSDRAMIRQEn);
//PRINT_L2("Exit \"L2_ClearIRQEn\"\n");
return L2K_SUCCESS;
}
//-----------------------------------------------------------------------------
//L2_GetIRQEn
//-----------------------------------------------------------------------------
/*
routine description:
Get IRQ Enable bits
arguments:
*pbmUSBIRQEn:
[0x00]: 0: IRQID_00 enable bit cleared 1: IRQID_00 enable bit set
[0x01]: 0: IRQID_01 enable bit cleared 1: IRQID_01 enable bit set
[0x02]: 0: IRQID_02 enable bit cleared 1: IRQID_02 enable bit set
[0x03]: 0: IRQID_03 enable bit cleared 1: IRQID_03 enable bit set
[0x04]: 0: IRQID_04 enable bit cleared 1: IRQID_04 enable bit set
[0x05]: 0: IRQID_05 enable bit cleared 1: IRQID_05 enable bit set
[0x06]: 0: IRQID_06 enable bit cleared 1: IRQID_06 enable bit set
[0x07]: 0: IRQID_07 enable bit cleared 1: IRQID_07 enable bit set
[0x08]: 0: IRQID_08 enable bit cleared 1: IRQID_08 enable bit set
[0x09]: 0: IRQID_09 enable bit cleared 1: IRQID_09 enable bit set
[0x0e]: 0: IRQID_0e enable bit cleared 1: IRQID_0e enable bit set
[0x0f]: 0: IRQID_0f enable bit cleared 1: IRQID_0f enable bit set
[0x10]: 0: IRQID_10 enable bit cleared 1: IRQID_10 enable bit set
[0x11]: 0: IRQID_11 enable bit cleared 1: IRQID_11 enable bit set
[0x12]: 0: IRQID_12 enable bit cleared 1: IRQID_12 enable bit set
[0x13]: 0: IRQID_13 enable bit cleared 1: IRQID_13 enable bit set
[0x14]: 0: IRQID_14 enable bit cleared 1: IRQID_14 enable bit set
[0x15]: 0: IRQID_15 enable bit cleared 1: IRQID_15 enable bit set
*pbmGlobalIRQEn:
[0]: 0: IRQID_20 enable bit cleared 1: IRQID_20 enable bit set
[1]: 0: IRQID_21 enable bit cleared 1: IRQID_21 enable bit set
[2]: 0: IRQID_22 enable bit cleared 1: IRQID_22 enable bit set
[3]: 0: IRQID_23 enable bit cleared 1: IRQID_23 enable bit set
[4]: 0: IRQID_24 enable bit cleared 1: IRQID_24 enable bit set
[5]: 0: IRQID_25 enable bit cleared 1: IRQID_25 enable bit set
[6]: 0: IRQID_26 enable bit cleared 1: IRQID_26 enable bit set
[7]: 0: IRQID_27 enable bit cleared 1: IRQID_27 enable bit set
*pbmSDRAMIRQEn:
[0]: 0: IRQID_30 enable bit cleared 1: IRQID_30 enable bit set
return value:
0x00 - success
others - error
*/
UCHAR L2_GetIRQEn(ULONG *pbmUSBIRQEn, UCHAR *pbmGlobalIRQEn, UCHAR *pbmSDRAMIRQEn) USING_0
{
//PRINT_L2("Enter \"L2_GetIRQEn\" \n");
*pbmUSBIRQEn = ((ULONG)XBYTE[0x25d2]<<16)|((ULONG)XBYTE[0x25d1]<<8)|(ULONG)XBYTE[0x25d0];
*pbmGlobalIRQEn = XBYTE[0x20d0];
*pbmSDRAMIRQEn = XBYTE[0x27d0];
//PRINT_L2("Exit \"L2_GetIRQEn\"\n");
return L2K_SUCCESS;
}
#ifdef TestModeEn
//-----------------------------------------------------------------------------
//L2_TestCDSP
//-----------------------------------------------------------------------------
/*
routine description:
CPU module test.
arguments:
TestLevel: the level of test
return value:
0x00 - success
others - error
*/
UCHAR L2_TestCPU(UCHAR TestLevel) USING_0
{
UCHAR status = L2K_SUCCESS;
UCHAR Temp0 = TestLevel;
return(status);
}
#endif
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