l2_global.c

dz3000_51.0.0.4.rar

/*++
Copyright (c) 2001 Sunplus Technology Co., Ltd.

Module Name:

        L2_glbal.c

Abstract:

        Module related to L2 CDSP functions

Environment:

        Keil C51 Compiler

Revision History:

        11/12/2001      CMLin    created
--*/
//=============================================================================
//Header file
//=============================================================================
#include "general.h"
//#include "main.h"

//=============================================================================
//Symbol
//=============================================================================
//-----------------------------------------------------------------------------
//Constant
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//Variable
//-----------------------------------------------------------------------------
sfr MemStretch = 0x8E;
extern void UI_PrintOSDString(PUCHAR str, UCHAR x, UCHAR y , UCHAR attrib);
extern void UI_PrintOSDNumber(USHORT num, UCHAR x, UCHAR y, UCHAR fillbit);
//=============================================================================
//Program
//=============================================================================
//-----------------------------------------------------------------------------
//L2_Suspend
//-----------------------------------------------------------------------------
/*
routine description:
    Put the SPCA533 into suspend mode. This function puts all internal analog
  macros into the power-down mode and stops the clocks. The GPIO is not
  handled by this function because the functions of the GPIO depend on
  the customer application.

arguments:
  Mode:
     0: normal
     1: reset the CPU if resumed

return value:
  0x00   - success
  0x01   - general error
  0x02   - parameter error
  others - error
*/

UCHAR L2_Suspend(UCHAR Mode) USING_0
{
  UCHAR status;
  UCHAR tmp;

  status = L2K_SUCCESS;

  //body
  //PRINT_L2("        L2_Suspend: Enter\n");
  /*
  tmp = MemStretch;
  MemStretch = 0x01;

  XBYTE[0x2530] = 0x01; //USB SRAM test enable
  XBYTE[0x2532] = 0x00; //USB SRAM page selection


  XBYTE[0x2001] = 0x0C; //power down TV encode
  XBYTE[0x2670] = 0x01; //power down audio ADC
  XBYTE[0x2675] = 0x00; //power down audio DAC
  XBYTE[0x2080] = 0x00; //power down TGPLL
  XBYTE[0x2006] = 0x01; //all DRAM pins are enalbed
  XBYTE[0x2708] = 0x01; //SDRAM self-refresh

  L2_SuspendFront();    //suspend front

  XBYTE[0x2030] = 0x00; //GPIO drive 0
  XBYTE[0x2031] = 0x00;
  XBYTE[0x2032] = 0x0c;
  XBYTE[0x2033] = 0x00;
  XBYTE[0x2034] = 0x00;
  XBYTE[0x2035] = 0x00;
  XBYTE[0x2038] = 0xFF;
  XBYTE[0x2039] = 0xFF;
  XBYTE[0x203A] = 0xFF;
  XBYTE[0x203B] = 0xFF;
  XBYTE[0x203C] = 0xFF;
  XBYTE[0x203D] = 0xFF;

  XBYTE[0x2400] = 0x00; //FMGPIO drive 0
  XBYTE[0x2401] = 0x00;
  XBYTE[0x2402] = 0x00;
  XBYTE[0x2403] = 0x00;
  XBYTE[0x2404] = 0x00;
  XBYTE[0x2405] = 0xFF;
  XBYTE[0x2406] = 0xFF;
  XBYTE[0x2407] = 0xFF;
  XBYTE[0x2408] = 0xFF;

  XBYTE[0x2D00] = 0x00; //TVGPIO drive 0
  XBYTE[0x2D71] = 0x00;
  XBYTE[0x2D72] = 0x00;
  XBYTE[0x2D73] = 0x00;
  XBYTE[0x2D74] = 0xFF;
  XBYTE[0x2D75] = 0xFF;
  XBYTE[0x2D76] = 0xFF;

  XBYTE[0x2048] = 0x00; //GPIO rising event interrupt
  XBYTE[0x2049] = 0x00;
  XBYTE[0x204A] = 0x00;
  XBYTE[0x204B] = 0x00;
  XBYTE[0x204C] = 0x00;
  XBYTE[0x204D] = 0x00;
  XBYTE[0x2050] = 0xFF;
  XBYTE[0x2051] = 0xFF;
  XBYTE[0x2052] = 0xFF;
  XBYTE[0x2053] = 0xFF;
  XBYTE[0x2054] = 0xFF;
  XBYTE[0x2055] = 0xFF;

  XBYTE[0x2078] = 0x00; //GPIO falling event interrupt
  XBYTE[0x2079] = 0x00;
  XBYTE[0x207A] = 0x00;
  XBYTE[0x207B] = 0x00;
  XBYTE[0x207C] = 0x00;
  XBYTE[0x207D] = 0x00;
  XBYTE[0x2058] = 0xFF;
  XBYTE[0x2059] = 0xFF;
  XBYTE[0x205A] = 0xFF;
  XBYTE[0x205B] = 0xFF;
  XBYTE[0x205C] = 0xFF;
  XBYTE[0x205D] = 0xFF;

  XBYTE[0x2418] = 0x00; //FMGPIO rising/falling event interrupt
  XBYTE[0x2419] = 0x00;
  XBYTE[0x241A] = 0x00;
  XBYTE[0x241B] = 0x00;
  XBYTE[0x241C] = 0x00;
  XBYTE[0x241D] = 0x00;
  XBYTE[0x241F] = 0x00;
  XBYTE[0x2410] = 0xFF;
  XBYTE[0x2411] = 0xFF;
  XBYTE[0x2412] = 0xFF;
  XBYTE[0x2413] = 0xFF;
  XBYTE[0x2415] = 0xFF;
  XBYTE[0x2416] = 0xFF;
  XBYTE[0x2417] = 0xFF;

  XBYTE[0x2DC1] = 0x00; //TVGPIO rising/falling event interrupt
  XBYTE[0x2DC2] = 0x00;
  XBYTE[0x2DC3] = 0x00;
  XBYTE[0x2DC4] = 0x00;
  XBYTE[0x2DC5] = 0x00;
  XBYTE[0x2DC6] = 0x00;
  XBYTE[0x2DD1] = 0xFF;
  XBYTE[0x2DD2] = 0xFF;
  XBYTE[0x2DD3] = 0xFF;
  XBYTE[0x2DD4] = 0xFF;
  XBYTE[0x2DD5] = 0xFF;
  XBYTE[0x2DD6] = 0xFF;


  /*
  P1 = 0x00;
  P3 = 0xC0;
  XBYTE[0x2C02] = 0xFF;
  XBYTE[0x2C03] = 0xFF;

  XBYTE[0x20C0] = 0x00; //global event interrupt
  XBYTE[0x20D0] = 0x03;

  XBYTE[0x23C0] = 0x00; //DMA event interrupt
  XBYTE[0x23D0] = 0x00;

  XBYTE[0x24C0] = 0x00; //storage media event interrupt
  XBYTE[0x24D0] = 0x00;

  XBYTE[0x25C0] = 0x00; //USB event interrupt
  XBYTE[0x25C1] = 0x00;
  XBYTE[0x25C2] = 0x00;
  XBYTE[0x25D0] = 0xFF;
  XBYTE[0x25D1] = 0x00;
  XBYTE[0x25D2] = 0x00;

  XBYTE[0x26C0] = 0x00; //Audio event interrupt
  XBYTE[0x26C1] = 0x00;
  XBYTE[0x26D0] = 0x00;
  XBYTE[0x26D1] = 0x00;

  XBYTE[0x27C0] = 0x00; //SDRAM event interrupt
  XBYTE[0x27D0] = 0x00;

  XBYTE[0x2DC0] = 0x00; //TVENC event interrupt
  XBYTE[0x2DD0] = 0x00;
  */

  XBYTE[0x2004] = 0x05; //resume length 5ms

  if(Mode==0x01)
    XBYTE[0x2003] = 0x03; //suspend and reset CPU when resume
  else
    XBYTE[0x2003] = 0x01; //suspend and don't reset CPU when resume

  MemStretch = tmp;

  // return
  //PRINT_L2("        L2_Suspend: Exit\n");

  return(status);
}

//-----------------------------------------------------------------------------
//L2_Resume
//-----------------------------------------------------------------------------
/*
routine description:
    Resume the operation of the SPCA533. It clears the related interrupt and puts
  all the IO pins back to the normal operation states. In firmware coding,
  this function must be called right after the Suspend function.

arguments:
  none

return value:
  none
*/

void L2_Resume(void) USING_0
{
  //body
  //PRINT_L2("        L2_Resume: Enter\n");

  XBYTE[0x2003] = 0x00; //clear swsuspend

/*
  XBYTE[0x2038] = 0x00; //GPIO tri-stated
  XBYTE[0x2039] = 0x00;
  XBYTE[0x203A] = 0x00;
  XBYTE[0x203B] = 0x00;
  XBYTE[0x203C] = 0x00;
  XBYTE[0x203D] = 0x00;

  XBYTE[0x2405] = 0x00; //FMGPIO tri-stated
  XBYTE[0x2406] = 0x00;
  XBYTE[0x2407] = 0x00;
  XBYTE[0x2408] = 0x00;

  XBYTE[0x2D74] = 0x00; //TVGPIO tri-stated
  XBYTE[0x2D75] = 0x00;
  XBYTE[0x2D76] = 0x00;

  XBYTE[0x2048] = 0x00; //GPIO rising event interrupt
  XBYTE[0x2049] = 0x00;
  XBYTE[0x204A] = 0x00;
  XBYTE[0x204B] = 0x00;
  XBYTE[0x204C] = 0x00;
  XBYTE[0x204D] = 0x00;
  XBYTE[0x2050] = 0x00;
  XBYTE[0x2051] = 0x00;
  XBYTE[0x2052] = 0x00;
  XBYTE[0x2053] = 0x00;
  XBYTE[0x2054] = 0x00;
  XBYTE[0x2055] = 0x00;

  XBYTE[0x2078] = 0x00; //GPIO falling event interrupt
  XBYTE[0x2079] = 0x00;
  XBYTE[0x207A] = 0x00;
  XBYTE[0x207B] = 0x00;
  XBYTE[0x207C] = 0x00;
  XBYTE[0x207D] = 0x00;
  XBYTE[0x2058] = 0x00;
  XBYTE[0x2059] = 0x00;
  XBYTE[0x205A] = 0x00;
  XBYTE[0x205B] = 0x00;
  XBYTE[0x205C] = 0x00;
  XBYTE[0x205D] = 0x00;

  XBYTE[0x2410] = 0x00; //FMGPIO rising/falling event interrupt
  XBYTE[0x2411] = 0x00;
  XBYTE[0x2412] = 0x00;
  XBYTE[0x2413] = 0x00;
  XBYTE[0x2415] = 0x00;
  XBYTE[0x2416] = 0x00;
  XBYTE[0x2417] = 0x00;

  XBYTE[0x2DD1] = 0x00; //TVGPIO rising/falling event interrupt
  XBYTE[0x2DD2] = 0x00;
  XBYTE[0x2DD3] = 0x00;
  XBYTE[0x2DD4] = 0x00;
  XBYTE[0x2DD5] = 0x00;
  XBYTE[0x2DD6] = 0x00;

  XBYTE[0x20D0] = 0x00; //global event interrupt

  XBYTE[0x25D0] = 0x00; //USB event interrupt
*/

  // return
  //PRINT_L2("        L2_Resume: Exit\n");

  return;
}

//-----------------------------------------------------------------------------
//L2_PowerDown
//-----------------------------------------------------------------------------
/*
routine description:
    Put the SPCA533 into power-down state. All analog building blocks are
  disabled (or powered-down). The internal clocks are gated. The CPU is
  operated at the lowest frequency.

arguments:
  none

return value:
  none
*/

void L2_PowerDown(void) USING_0
{
  //body
  //PRINT_L2("        L2_PowerDown: Enter\n");

  XBYTE[0x2001] = 0x0C; //power down TV encode
  XBYTE[0x2013] = 0x00; //gate phase clock
  XBYTE[0x2080] = 0x00; //power down TGPLL

  XBYTE[0x2670] = 0x01; //power down audio ADC
  XBYTE[0x2675] = 0x00; //power down audio DAC

  XBYTE[0x2024] = 0x07; //CPU operating frequency: 375 kHz

  // return
  //PRINT_L2("        L2_PowerDown: Exit\n");

  return;
}

//-----------------------------------------------------------------------------
//L2_SetModuPowerDown
//-----------------------------------------------------------------------------
/*
routine description:
    Put the module to power down mode. The function puts the analog macros of
  the module into power-down mode and stops the clocks of the module.

arguments:
  ModuSel:
    Bit 0: sensor interface controller
    Bit 1: color DSP
    Bit 2: DRAM controller
    Bit 3: LCD/TV interface controller
    Bit 4: storage media controller
    Bit 5: audio controller
    Bit 6: USB controller
    Bit 7: DMA
    Bit 8: JPEG engine

return value:
  0x00   - success
  0x01   - general error
  0x02   - parameter error
  others - error
*/

UCHAR L2_SetModuPowerDown(USHORT ModuSel) USING_0
{
  UCHAR tmp0, tmp1;
  UCHAR status;

  status = L2K_SUCCESS;

  //body
  //PRINT_L2("        L2_SetModuPowerDown: Enter\n");

  tmp0 = M_LoByteOfWord(ModuSel);
  tmp1 = M_HiByteOfWord(ModuSel);

  if(tmp0&0x01)
  {
    XBYTE[0x2007] = 0x00; //all TG pins are tri-stated
    XBYTE[0x2008] = 0x00;
    XBYTE[0x2009] = 0x00;
    XBYTE[0x200A] = 0xFF; //all TG input are gated
    XBYTE[0x200B] = 0xFF;

    XBYTE[0x2080] = 0x00; //power down TGPLL

    XBYTE[0x2012] &= 0xFE; //gate b1xck on the front module
  }

  if(tmp0&0x02)
  {
    XBYTE[0x2010] &= 0xFE; //gate clk48m on the CDSP module
    XBYTE[0x2012] &= 0xFD; //gate b1xck on the CDSP module
  }

  if(tmp0&0x04)
  {
    XBYTE[0x2010] &= 0xDF; //gate clk48m on the SDRAM module
  }

  if(tmp0&0x08)
  {
    XBYTE[0x2001] = 0x0C; //power down TV encode

    XBYTE[0x2010] &= 0x7F; //gate clk48m on the TVENC module
    XBYTE[0x2013] &= 0xE7; //gate ptvenc1xck and ptvenc2xck
  }

  if(tmp0&0x10)
  {
    XBYTE[0x2010] &= 0xFB; //gate clk48m on the storage media module
  }

  if(tmp0&0x20)
  {
    XBYTE[0x2670] = 0x01; //power down audio ADC
    XBYTE[0x2675] = 0x00; //power down audio DAC

    XBYTE[0x2010] &= 0xEF; //gate clk48m on the audio module
    XBYTE[0x2011] &= 0xFD; //gate uclk on the audio module
    XBYTE[0x2013] &= 0x7F; //gate pauclk
  }

  if(tmp0&0x40)
  {
    XBYTE[0x2005] = 0x00; //disable internal USB transceiver

    XBYTE[0x2011] &= 0xFE; //gate uclk on the USB module
    XBYTE[0x2010] &= 0xF7; //gate clk48m on the USB module
  }

  if(tmp0&0x80)
  {
    XBYTE[0x2010] &= 0xFD; //gate clk48m on the DMA module
  }

  if(tmp1&0x01)
  {
    XBYTE[0x2010] &= 0xBF; //gate clk48m on the JPEG module
  }

  // return
  //PRINT_L2("        L2_SetModuPowerDown: Exit\n");

  return(status);
}

//-----------------------------------------------------------------------------
//L2_SetCPUClock
//-----------------------------------------------------------------------------
/*
routine description:
    Set the CPU clock frequency. The setting of lower frequency is for the
  power saving issue and the higher setting of frequency is for the
  performance issue.  The access time of CPU ROM must be fast enough
  when the higher frequency is selected.

arguments:
  FreqSel:
  	0:  32 MHz
        1:  24 MHz
        2:  12 MHz
        3:   6 MHz
        4:   3 MHz
        5: 1.5 MHz
        6: 750 KHz
        7: 375 KHz

return value:
  0x00   - success
  0x01   - general error
  0x02   - parameter error
  others - error
*/

UCHAR L2_SetCPUClock(UCHAR FreqSel) USING_0
{
  UCHAR status;

  status = L2K_SUCCESS;

  //body
  //PRINT_L2("        L2_SetCPUClock: Enter\n");

  XBYTE[0x2024] = FreqSel;

  // return
  //PRINT_L2("        L2_SetCPUClock: Exit\n");

  return(status);
}

//-----------------------------------------------------------------------------
//L2_PowerUp
//-----------------------------------------------------------------------------
/*
routine description:
    Restore the SPCA533 back to power-up state. The internal clocks are enabled.
  The CPU is operated at 24 MHz.

arguments:
  none

return value:
  none
*/

void L2_PowerUp(void) USING_0
{
  //body
  //PRINT_L2("        L2_PowerUp: Enter\n");

  XBYTE[0x2013] = 0xff; //enable phase clock

  XBYTE[0x2024] = 0x01; //CPU operating frequency: 24 MHz

  // return
  //PRINT_L2("        L2_PowerUp: Exit\n");

  return;
}

//-----------------------------------------------------------------------------
//L2_SetModuPowerUp
//-----------------------------------------------------------------------------
/*
routine description:
    Restore the module back to normal operation mode. The function enables the
  clocks of the module.

arguments:
  ModuSel:
    Bit 0: sensor interface controller
    Bit 1: color DSP
    Bit 2: DRAM controller
    Bit 3: LCD/TV interface controller
    Bit 4: storage media controller
    Bit 5: audio controller
    Bit 6: USB controller
    Bit 7: DMA
    Bit 8: JPEG engine

return value:
  0x00   - success
  0x01   - general error
  0x02   - parameter error
  others - error
*/

UCHAR L2_SetModuPowerUp(USHORT ModuSel) USING_0
{
  UCHAR tmp0, tmp1;
  UCHAR status;

  status = L2K_SUCCESS;

  //body
  //PRINT_L2("        L2_SetModuPowerUp: Enter\n");

  tmp0 = M_LoByteOfWord(ModuSel);
  tmp1 = M_HiByteOfWord(ModuSel);

  if(tmp0&0x01)
  {
    XBYTE[0x200a] = 0xff; //all TG input are enabled
    XBYTE[0x200f] = 0xff;

    XBYTE[0x2012] |= 0x01; //enable b1xck on the front module
  }

  if(tmp0&0x02)
  {
    XBYTE[0x2010] |= 0x01; //enable clk48m on the CDSP module
    XBYTE[0x2012] |= 0x02; //enable b1xck on the CDSP module
  }

  if(tmp0&0x04)
  {
    XBYTE[0x2010] |= 0x20; //enable clk48m on the SDRAM module
  }

  if(tmp0&0x08)
  {
    XBYTE[0x2010] |= 0x80; //enable clk48m on the TVENC module
    XBYTE[0x2013] |= 0x18; //enable ptvenc1xck and ptvenc2xck
  }

  if(tmp0&0x10)
  {
    XBYTE[0x2010] |= 0x04; //enable clk48m on the storage media module
  }

  if(tmp0&0x20)
  {
    XBYTE[0x2010] |= 0x80; //enable clk48m on the audio module
    XBYTE[0x2011] |= 0x02; //enable uclk on the audio module
    XBYTE[0x2013] |= 0x80; //enable pauclk
  }

  if(tmp0&0x40)
  {
    XBYTE[0x2005] = 0x01; //enable internal USB transceiver

    XBYTE[0x2011] |= 0x01; //enable uclk on the USB module
    XBYTE[0x2010] |= 0x08; //enable clk48m on the USB module
  }