usb_int.txt

stm32.rar

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 942] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Int_Flash\usb_int.o --depend=.\Int_Flash\usb_int.d --device=DARMSTM --apcs=interwork -O3 -I..\include -I..\..\..\..\..\INC\ST\STM32F10x\USB -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB --omf_browse=.\Int_Flash\usb_int.crf ..\..\..\..\..\RV31\LIB\ST\STM32F10x\USB\usb_int.c]
                          THUMB

                          AREA ||i.CTR_LP||, CODE, READONLY, ALIGN=2

                  CTR_LP PROC
;;;41     void CTR_LP(void)
;;;42     {
000000  e92d5ff0          PUSH     {r4-r12,lr}
000004  f64b768f          MOV      r6,#0xbf8f
000008  f64877bf          MOV      r7,#0x8fbf
00000c  f8df8158          LDR      r8,|L1.360|
000010  f6407a8f          MOV      r10,#0xf8f
000014  f8df9154          LDR      r9,|L1.364|
000018  f6487b0f          MOV      r11,#0x8f0f
00001c  4c54              LDR      r4,|L1.368|
;;;43       u32 wEPVal = 0;
;;;44       /* stay in loop while pending ints */
;;;45       while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
00001e  e09b              B        |L1.344|
                  |L1.32|
;;;46       {
;;;47         _SetISTR((u16)CLR_CTR); /* clear CTR flag */
000020  f64770ff          MOV      r0,#0x7fff
000024  f8c40c44          STR      r0,[r4,#0xc44]
;;;48         /* extract highest priority endpoint number */
;;;49         EPindex = (u8)(wIstr & ISTR_EP_ID);
000028  8808              LDRH     r0,[r1,#0]  ; wIstr
00002a  f000000f          AND      r0,r0,#0xf
00002e  f8890000          STRB     r0,[r9,#0]  ; EPindex
;;;50         if (EPindex == 0)
000032  b2c0              UXTB     r0,r0
000034  2800              CMP      r0,#0
000036  d168              BNE      |L1.266|
000038  f5046440          ADD      r4,r4,#0xc00
;;;51         {
;;;52           /* Decode and service control endpoint interrupt */
;;;53           /* calling related service routine */
;;;54           /* (Setup0_Process, In0_Process, Out0_Process) */
;;;55     
;;;56           /* save RX & TX status */
;;;57           /* and set both to NAK */
;;;58           SaveRState = _GetEPRxStatus(ENDP0);
00003c  6820              LDR      r0,[r4,#0]
00003e  f3c03001          UBFX     r0,r0,#12,#2
000042  0300              LSLS     r0,r0,#12
000044  f8a80000          STRH     r0,[r8,#0]  ; SaveRState
;;;59           SaveTState = _GetEPTxStatus(ENDP0);
000048  6820              LDR      r0,[r4,#0]
00004a  f3c01001          UBFX     r0,r0,#4,#2
00004e  0100              LSLS     r0,r0,#4
000050  f8a80002          STRH     r0,[r8,#2]  ; SaveTState
;;;60           _SetEPRxStatus(ENDP0, EP_RX_NAK);
000054  6820              LDR      r0,[r4,#0]
000056  b280              UXTH     r0,r0
000058  4030              ANDS     r0,r0,r6
00005a  f4805000          EOR      r0,r0,#0x2000
00005e  6020              STR      r0,[r4,#0]
;;;61           _SetEPTxStatus(ENDP0, EP_TX_NAK);
000060  6820              LDR      r0,[r4,#0]
000062  b280              UXTH     r0,r0
000064  4038              ANDS     r0,r0,r7
000066  f0800020          EOR      r0,r0,#0x20
00006a  6020              STR      r0,[r4,#0]
;;;62     
;;;63     
;;;64           /* DIR bit = origin of the interrupt */
;;;65     
;;;66           if ((wIstr & ISTR_DIR) == 0)
00006c  8808              LDRH     r0,[r1,#0]  ; wIstr
00006e  f5a46440          SUB      r4,r4,#0xc00          ;61
000072  06c0              LSLS     r0,r0,#27
000074  d504              BPL      |L1.128|
;;;67           {
;;;68             /* DIR = 0 */
;;;69     
;;;70             /* DIR = 0      => IN  int */
;;;71             /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
;;;72     
;;;73     
;;;74             _ClearEP_CTR_TX(ENDP0);
;;;75             In0_Process();
;;;76     
;;;77                /* before terminate set Tx & Rx status */
;;;78               _SetEPRxStatus(ENDP0, SaveRState);
;;;79               _SetEPTxStatus(ENDP0, SaveTState);
;;;80               return;
;;;81           }
;;;82           else
;;;83           {
;;;84             /* DIR = 1 */
;;;85     
;;;86             /* DIR = 1 & CTR_RX       => SETUP or OUT int */
;;;87             /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
;;;88     
;;;89             wEPVal = _GetENDPOINT(ENDP0);
000076  f8d40c00          LDR      r0,[r4,#0xc00]
00007a  b280              UXTH     r0,r0
;;;90             if ((wEPVal & EP_CTR_TX) != 0)
00007c  0601              LSLS     r1,r0,#24
00007e  d51f              BPL      |L1.192|
                  |L1.128|
000080  f8d40c00          LDR      r0,[r4,#0xc00]        ;74
000084  b280              UXTH     r0,r0                 ;74
000086  ea00000b          AND      r0,r0,r11             ;74
00008a  f8c40c00          STR      r0,[r4,#0xc00]        ;74
00008e  f7fffffe          BL       In0_Process
000092  e02c              B        |L1.238|
                  |L1.148|
000094  0489              LSLS     r1,r1,#18             ;78
000096  d501              BPL      |L1.156|
000098  f4805000          EOR      r0,r0,#0x2000         ;78
                  |L1.156|
;;;91             {
;;;92               _ClearEP_CTR_TX(ENDP0);
;;;93               In0_Process();
;;;94               /* before terminate set Tx & Rx status */
;;;95               _SetEPRxStatus(ENDP0, SaveRState);
;;;96               _SetEPTxStatus(ENDP0, SaveTState);
;;;97               return;
;;;98             }
;;;99             else if ((wEPVal &EP_SETUP) != 0)
;;;100            {
;;;101              _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
;;;102              Setup0_Process();
;;;103              /* before terminate set Tx & Rx status */
;;;104              _SetEPRxStatus(ENDP0, SaveRState);
;;;105              _SetEPTxStatus(ENDP0, SaveTState);
;;;106              return;
;;;107            }
;;;108    
;;;109            else if ((wEPVal & EP_CTR_RX) != 0)
;;;110            {
;;;111              _ClearEP_CTR_RX(ENDP0);
;;;112              Out0_Process();
;;;113              /* before terminate set Tx & Rx status */
;;;114              _SetEPRxStatus(ENDP0, SaveRState);
00009c  f8c40c00          STR      r0,[r4,#0xc00]
;;;115              _SetEPTxStatus(ENDP0, SaveTState);
0000a0  f8d40c00          LDR      r0,[r4,#0xc00]
0000a4  f8b81002          LDRH     r1,[r8,#2]  ; SaveTState
0000a8  b280              UXTH     r0,r0
0000aa  4038              ANDS     r0,r0,r7
0000ac  06ca              LSLS     r2,r1,#27
0000ae  d429              BMI      |L1.260|
                  |L1.176|
0000b0  0689              LSLS     r1,r1,#26             ;79
0000b2  d501              BPL      |L1.184|
0000b4  f0800020          EOR      r0,r0,#0x20           ;79
                  |L1.184|
0000b8  f8c40c00          STR      r0,[r4,#0xc00]
                  |L1.188|
;;;116              return;
;;;117            }
;;;118          }
;;;119        }/* if(EPindex == 0) */
;;;120        else
;;;121        {
;;;122          /* Decode and service non control endpoints interrupt  */
;;;123    
;;;124          /* process related endpoint register */
;;;125          wEPVal = _GetENDPOINT(EPindex);
;;;126          if ((wEPVal & EP_CTR_RX) != 0)
;;;127          {
;;;128            /* clear int flag */
;;;129            _ClearEP_CTR_RX(EPindex);
;;;130    
;;;131            /* call OUT service function */
;;;132            (*pEpInt_OUT[EPindex-1])();
;;;133    
;;;134          } /* if((wEPVal & EP_CTR_RX) */
;;;135    
;;;136          if ((wEPVal & EP_CTR_TX) != 0)
;;;137          {
;;;138            /* clear int flag */
;;;139            _ClearEP_CTR_TX(EPindex);
;;;140    
;;;141            /* call IN service function */
;;;142            (*pEpInt_IN[EPindex-1])();
;;;143          } /* if((wEPVal & EP_CTR_TX) != 0) */
;;;144    
;;;145        }/* if(EPindex == 0) else */
;;;146