📄 enc28j60.lst
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243 1 enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
244 1
245 1 // TODO, fix this up
246 1
247 1 if( uip_len <= TOTAL_HEADER_LENGTH )
248 1 {
249 2 // copy the packet into the transmit buffer
250 2 enc28j60WriteBuffer(len, packet);
251 2 }
252 1 else
253 1 {
254 2 len -= TOTAL_HEADER_LENGTH;
255 2 enc28j60WriteBuffer(TOTAL_HEADER_LENGTH, packet);
256 2 enc28j60WriteBuffer(len, (unsigned char *)uip_appdata);
257 2 }
258 1
259 1
260 1
261 1 //
262 1 // Errata workaround #12, reset TX logic
263 1 //
264 1 {
265 2 // clear TXRST bit in ECON1
266 2 //enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
267 2 //delay(100);
268 2 // set TXRST bit in ECON1
269 2 //enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
270 2 }
271 1 // send the contents of the transmit buffer onto the network
272 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
273 1 }
274
275
276
277
278 u16_t enc28j60PacketReceive(u16_t maxlen, u8_t* packet)
279 {
280 1 u16_t rxstat;
281 1 u16_t len;
282 1
283 1 // check if a packet has been received and buffered
284 1 if( !(enc28j60Read(EIR) & EIR_PKTIF) )
285 1 {
286 2 // Errata workaround #6, PKTIF is not reliable
287 2 // double check by looking at EPKTCNT
288 2 if (enc28j60Read(EPKTCNT) == 0)
289 2 return 0;
290 2 }
291 1
292 1 // Make absolutely certain that any previous packet was discarded
293 1 //if( WasDiscarded == FALSE)
294 1 // MACDiscardRx();
295 1
296 1 // Set the read pointer to the start of the received packet
297 1 enc28j60Write(ERDPTL, (NextPacketPtr));
298 1 enc28j60Write(ERDPTH, (NextPacketPtr)>>8);
299 1
300 1 // read the next packet pointer
301 1 NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
302 1 NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
C51 COMPILER V8.15 ENC28J60 08/11/2009 15:07:52 PAGE 6
303 1
304 1 // read the packet length
305 1 len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
306 1 len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
307 1
308 1 // read the receive status
309 1 rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
310 1 rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
311 1
312 1 // limit retrieve length
313 1 // (we reduce the MAC-reported length by 4 to remove the CRC)
314 1 len = MIN(len, maxlen);
315 1
316 1 // copy the packet from the receive buffer
317 1 enc28j60ReadBuffer(len, packet);
318 1
319 1 // Move the RX read pointer to the start of the next received packet
320 1 // This frees the memory we just read out
321 1 /*
322 1 enc28j60Write(ERXRDPTL, (NextPacketPtr));
323 1 enc28j60Write(ERXRDPTH, (NextPacketPtr)>>8);
324 1 */
325 1 // Errata workaround #13. Make sure ERXRDPT is odd
326 1 //
327 1 {
328 2 u16_t rs,re;
329 2 rs = enc28j60Read(ERXSTH);
330 2 rs <<= 8;
331 2 rs |= enc28j60Read(ERXSTL);
332 2 re = enc28j60Read(ERXNDH);
333 2 re <<= 8;
334 2 re |= enc28j60Read(ERXNDL);
335 2 if (NextPacketPtr - 1 < rs || NextPacketPtr - 1 > re)
336 2 {
337 3 enc28j60Write(ERXRDPTL, (re));
338 3 enc28j60Write(ERXRDPTH, (re)>>8);
339 3 }
340 2 else
341 2 {
342 3 enc28j60Write(ERXRDPTL, (NextPacketPtr-1));
343 3 enc28j60Write(ERXRDPTH, (NextPacketPtr-1)>>8);
344 3 }
345 2 }
346 1
347 1 // decrement the packet counter indicate we are done with this packet
348 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
349 1
350 1 return len;
351 1 }
352
353 void dev_init(void)
354 {
355 1 enc28j60_init();
356 1 }
357
358 void dev_send(void)
359 {
360 1 enc28j60PacketSend(uip_len, uip_buf);
361 1 }
362
363 u16_t dev_poll(void)
364 {
C51 COMPILER V8.15 ENC28J60 08/11/2009 15:07:52 PAGE 7
365 1 return enc28j60PacketReceive(UIP_BUFSIZE, uip_buf);
366 1 }
367
368 void enc28j60_init(void)
369 {
370 1
371 1
372 1 // perform system reset
373 1 enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
374 1 // delay(50);
375 1 // check CLKRDY bit to see if reset is complete
376 1 //while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
377 1 // Errata workaround #2, CLKRDY check is unreliable, delay 1 mS instead
378 1 delay_ms(5);
379 1
380 1 // lamp test
381 1 // enc28j60PhyWrite(PHLCON, 0x0AA2);
382 1
383 1
384 1
385 1 // do bank 0 stuff
386 1 // initialize receive buffer
387 1 // 16-bit transfers, must write low byte first
388 1
389 1 // set receive buffer start address
390 1 NextPacketPtr = RXSTART_INIT;
391 1 enc28j60Write(ERXSTL, RXSTART_INIT&0xFF);
392 1 enc28j60Write(ERXSTH, RXSTART_INIT>>8);
393 1
394 1 // set receive pointer address
395 1 enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF);
396 1 enc28j60Write(ERXRDPTH, RXSTART_INIT>>8);
397 1
398 1 // set receive buffer end
399 1 // ERXND defaults to 0x1FFF (end of ram)
400 1 enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF);
401 1 enc28j60Write(ERXNDH, RXSTOP_INIT>>8);
402 1
403 1 // set transmit buffer start
404 1 // ETXST defaults to 0x0000 (beginnging of ram)
405 1 enc28j60Write(ETXSTL, TXSTART_INIT&0xFF);
406 1 enc28j60Write(ETXSTH, TXSTART_INIT>>8);
407 1
408 1 // do bank 2 stuff
409 1 // enable MAC receive
410 1 enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
411 1 // bring MAC out of reset
412 1 enc28j60Write(MACON2, 0x00);
413 1 // enable automatic padding and CRC operations
414 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
415 1 // enc28j60Write(MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
416 1 // set inter-frame gap (non-back-to-back)
417 1 enc28j60Write(MAIPGL, 0x12);
418 1 enc28j60Write(MAIPGH, 0x0C);
419 1 // set inter-frame gap (back-to-back)
420 1 enc28j60Write(MABBIPG, 0x12);
421 1 // Set the maximum packet size which the controller will accept
422 1 enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF);
423 1 enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8);
424 1
425 1 // do bank 3 stuff
426 1 // write MAC address
C51 COMPILER V8.15 ENC28J60 08/11/2009 15:07:52 PAGE 8
427 1 // NOTE: MAC address in ENC28J60 is byte-backward
428 1 enc28j60Write(MAADR5, UIP_ETHADDR0);
429 1 enc28j60Write(MAADR4, UIP_ETHADDR1);
430 1 enc28j60Write(MAADR3, UIP_ETHADDR2);
431 1 enc28j60Write(MAADR2, UIP_ETHADDR3);
432 1 enc28j60Write(MAADR1, UIP_ETHADDR4);
433 1 enc28j60Write(MAADR0, UIP_ETHADDR5);
434 1
435 1 // no loopback of transmitted frames
436 1 enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
437 1 enc28j60PhyWrite(PHLCON,0x0472);
438 1
439 1 enc28j60Write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN); //D2 =0xb0
440 1 // switch to bank 0
441 1 enc28j60SetBank(ECON1);
442 1 // enable interrutps
443 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
444 1 // enable packet reception
445 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
446 1 /*
447 1 enc28j60PhyWrite(PHLCON, 0x0AA2);
448 1
449 1 // setup duplex ----------------------
450 1
451 1 // Disable receive logic and abort any packets currently being transmitted
452 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS|ECON1_RXEN);
453 1
454 1 {
455 1 uint16_t temp;
456 1 // Set the PHY to the proper duplex mode
457 1 temp = enc28j60PhyRead(PHCON1);
458 1 temp &= ~PHCON1_PDPXMD;
459 1 enc28j60PhyWrite(PHCON1, temp);
460 1 // Set the MAC to the proper duplex mode
461 1 temp = enc28j60Read(MACON3);
462 1 temp &= ~MACON3_FULDPX;
463 1 enc28j60Write(MACON3, temp);
464 1 }
465 1
466 1 // Set the back-to-back inter-packet gap time to IEEE specified
467 1 // requirements. The meaning of the MABBIPG value changes with the duplex
468 1 // state, so it must be updated in this function.
469 1 // In full duplex, 0x15 represents 9.6us; 0x12 is 9.6us in half duplex
470 1 //enc28j60Write(MABBIPG, DuplexState ? 0x15 : 0x12);
471 1
472 1 // Reenable receive logic
473 1 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
474 1
475 1 // setup duplex ----------------------
476 1 */
477 1 }
478
479
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1230 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- 38
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = 3 2
C51 COMPILER V8.15 ENC28J60 08/11/2009 15:07:52 PAGE 9
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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