📄 bias.out.1
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**** 11/05/05 23:06:24 ******* PSpice 10.3.0 (Jan 2004) ******* ID# 1111111111
** Profile: "Astable generator-bias" [ D:\CHRISTOPHE\LIVRES\SPICE SIMUS 2\Chapter4\Simulation examples\PSpice\Chapter 4-PSpiceFiles
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "bias.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of d:\OrCAD_10.3\tools\PSpice\PSpice.ini file:
.lib "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\copec.lib"
.lib "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\freerun.lib"
.lib "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\pwmswitch.lib"
.lib "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\application.lib"
.lib "nom.lib"
*Analysis directives:
.TRAN 0 100u 0 50n
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\Astable generator.net"
**** INCLUDING "Astable generator.net" ****
* source CHAPTER 4
X_U10 CT 0 CLOCK 0 SWHYSTE PARAMS: RON=200 ROFF=1Meg VT=3 VH=1
X_U11 CT N736919 CLOCK COMPARHYS PARAMS: VHIGH=5 VLOW=100M VHYS=2
V_V1 N736919 0 3
I_I1 0 CT DC 200u
C_C1 0 CT 1n
**** RESUMING bias.cir ****
.END
WARNING -- Library file "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\copec.lib" has changed since index file copec.ind was created.
WARNING -- The timestamp changed from Thu Aug 18 12:02:49 2005 to Thu Aug 18 11:02:49 2005.
Making new index file copec.ind for library file copec.lib
Index has 6 entries from 1 file(s).
WARNING -- Library file "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\freerun.lib" has changed since index file freerun.ind was created.
WARNING -- The timestamp changed from Wed Aug 17 01:00:41 2005 to Wed Aug 17 00:00:41 2005.
Making new index file freerun.ind for library file freerun.lib
Index has 26 entries from 1 file(s).
WARNING -- Library file "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\pwmswitch.lib" has changed since index file pwmswitch.ind was created.
WARNING -- The timestamp changed from Thu Aug 25 23:52:11 2005 to Thu Aug 25 22:52:11 2005.
Making new index file pwmswitch.ind for library file pwmswitch.lib
Index has 15 entries from 1 file(s).
WARNING -- Library file "D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\application.lib" has changed since index file application.ind was created.
WARNING -- The timestamp changed from Fri Aug 26 23:30:55 2005 to Sat Nov 05 22:49:16 2005.
Making new index file application.ind for library file application.lib
WARNING -- Duplicate library entry for AMPSIMP, (type SUBCKT)
First entry in D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\application.lib, duplicate in D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\application.lib.
Duplicate entry ignored.
Index has 20 entries from 1 file(s).
**** 11/05/05 23:06:24 ******* PSpice 10.3.0 (Jan 2004) ******* ID# 1111111111
** Profile: "Astable generator-bias" [ D:\CHRISTOPHE\LIVRES\SPICE SIMUS 2\Chapter4\Simulation examples\PSpice\Chapter 4-PSpiceFiles
**** Voltage Controlled Switch MODEL PARAMETERS
******************************************************************************
X_U10.smoothSW
RON 200
ROFF 1.000000E+06
VON 1
VOFF 0
ERROR -- Convergence problem in transient bias point calculation
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( CT) 10.8910 (CLOCK) 2.4769 (N736919) 1.4862
(X_U10.8) 0.0000 (X_U11.4) 2.4770
(X_U10.ref) 1.9816 (X_U11.HYS) 10.8910
(X_U10.ref1) 1.9816
These voltages failed to converge:
V(CT) = -8.907V \ 10.89V
V(X_U10.8) = 495.39mV \ 0V
V(X_U11.HYS) = -8.907V \ 10.89V
These supply currents failed to converge:
I(X_U10.EBcrtl) = -49.54nA \ 0A
These devices failed to converge:
X_U11.E1
Try running with .OPTION STEPGMIN
**** Interrupt ****
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