2407c.h

2407例程.rar

/*************************************************************************
/* File name: 2407c.h
/*
/* Description: 240x register definitions, Bit codes for BIT instruction
/*************************************************************************

/* 240x CPU core registers*/

unsigned int *IMR       =   (unsigned int *)0x0004; /* Interrupt Mask Register*/
unsigned int *IFR       =   (unsigned int *)0x0006; /* Interrupt Flag Register*/

/* System configuration and interrupt registers*/

unsigned int *SCSR1         =   (unsigned int *)0x7018; /* System Control & Status register. 1 */
unsigned int *SCSR2         =   (unsigned int *)0x7019; /* System Control & Status register. 2*/
unsigned int *DINR      =   (unsigned int *)0x701C; /* Device Identification Number register. */
unsigned int *PIVR      =   (unsigned int *)0x701E; /* Peripheral Interrupt Vector register. */
unsigned int *PIRQR0        =   (unsigned int *)0x7010; /* Peripheral Interrupt Request register 0*/
unsigned int *PIRQR1        =   (unsigned int *)0x7011; /* Peripheral Interrupt Request register 1*/
unsigned int *PIRQR2        =   (unsigned int *)0x7012; /* Peripheral Interrupt Request register 2*/
unsigned int *PIACKR0   =   (unsigned int *)0x7014; /* Peripheral Interrupt Acknowledge register 0 */
unsigned int *PIACKR1   =   (unsigned int *)0x7015; /* Peripheral Interrupt Acknowledge register 1 */
unsigned int *PIACKR2   =   (unsigned int *)0x7016; /* Peripheral Interrupt Acknowledge register 2*/

/* External interrupt configuration registers */

unsigned int *XINT1CR   =   (unsigned int *)0x7070; /* External interrupt 1 control register*/
unsigned int *XINT2CR   =   (unsigned int *)0x7071; /* External interrupt 2 control register*/

/* Digital I/O registers*/

unsigned int *MCRA=(unsigned int *)0x7090;  /* I/O Mux Control Register A*/
unsigned int *MCRB      =   (unsigned int *)0x7092; /* I/O Mux Control Register B*/
unsigned int *MCRC      =   (unsigned int *)0x7094; /* I/O Mux Control Register C*/
unsigned int *PADATDIR  =   (unsigned int *)0x7098; /* I/O port A Data & Direction register*/
unsigned int *PBDATDIR  =   (unsigned int *)0x709A; /* I/O port B Data & Direction register*/
unsigned int *PCDATDIR  =   (unsigned int *)0x709C; /* I/O port C Data & Direction register*/
unsigned int *PDDATDIR  =   (unsigned int *)0x709E; /* I/O port D Data & Direction register*/
unsigned int *PEDATDIR  =   (unsigned int *)0x7095; /* I/O port E Data & Direction register*/
unsigned int *PFDATDIR  =   (unsigned int *)0x7096; /* I/O port F Data & Direction register*/

/* Watchdog (WD) registers*/

unsigned int *WDCNTR        =   (unsigned int *)0x7023; /* WD Counter register */
unsigned int *WDKEY         =   (unsigned int *)0x7025; /* WD Key register*/
unsigned int *WDCR      =   (unsigned int *)0x7029; /* WD Control register*/

/* ADC registers*/

unsigned int *ADCTRL1   =   (unsigned int *)0x70A0; /* ADC Control register 1*/
unsigned int *ADCTRL2   =   (unsigned int *)0x70A1; /* ADC Control register 2*/
unsigned int *MAXCONV   =   (unsigned int *)0x70A2; /* Maximum conversion channels register*/
unsigned int *CHSELSEQ1 =   (unsigned int *)0x70A3; /* Channel select Sequencing control register 1*/
unsigned int *CHSELSEQ2     =   (unsigned int *)0x70A4; /* Channel select Sequencing control register 2*/
unsigned int *CHSELSEQ3     =   (unsigned int *)0x70A5; /* Channel select Sequencing control register 3*/
unsigned int *CHSELSEQ4     =   (unsigned int *)0x70A6; /* Channel select Sequencing control register 4*/
unsigned int *AUTO_SEQ_SR = (unsigned int *)0x70A7; /* Auto杝equence status register*/
unsigned int *RESULT0   =   (unsigned int *)0x70A8; /* Conversion result buffer register 0*/
unsigned int *RESULT1   =   (unsigned int *)0x70A9; /* Conversion result buffer register 1*/
unsigned int *RESULT2   =   (unsigned int *)0x70Aa; /* Conversion result buffer register 2*/
unsigned int *RESULT3   =   (unsigned int *)0x70Ab; /* Conversion result buffer register 3 */
unsigned int *RESULT4   =   (unsigned int *)0x70Ac; /* Conversion result buffer register 4*/
unsigned int *RESULT5   =   (unsigned int *)0x70Ad; /* Conversion result buffer register 5*/
unsigned int *RESULT6   =   (unsigned int *)0x70Ae; /* Conversion result buffer register 6*/
unsigned int *RESULT7   =   (unsigned int *)0x70Af; /* Conversion result buffer register 7*/
unsigned int *RESULT8   =   (unsigned int *)0x70B0; /* Conversion result buffer register 8*/
unsigned int *RESULT9   =   (unsigned int *)0x70B1; /* Conversion result buffer register 9 */
unsigned int *RESULT10  =   (unsigned int *)0x70B2; /* Conversion result buffer register 10*/
unsigned int *RESULT11  =   (unsigned int *)0x70B3; /* Conversion result buffer register 11*/
unsigned int *RESULT12  =   (unsigned int *)0x70B4; /* Conversion result buffer register 12*/
unsigned int *RESULT13  =   (unsigned int *)0x70B5; /* Conversion result buffer register 13*/
unsigned int *RESULT14  =   (unsigned int *)0x70B6; /* Conversion result buffer register 14*/
unsigned int *RESULT15  =   (unsigned int *)0x70B7; /* Conversion result buffer register 15*/
unsigned int *CALIBRATION   =   (unsigned int *)0x70B8; /* Calib result, used to correct*/
                /* subsequent conversions*/


/* SPI registers*/

unsigned int *SPICCR        =   (unsigned int *)0x7040; /* SPI Config Control register*/
unsigned int *SPICTL        =   (unsigned int *)0x7041; /* SPI Operation Control register*/
unsigned int *SPISTS        =   (unsigned int *)0x7042; /* SPI Status register*/
unsigned int *SPIBRR        =   (unsigned int *)0x7044; /* SPI Baud rate control register*/
unsigned int *SPIRXEMU  =   (unsigned int *)0x7046; /* SPI Emulation buffer register*/
unsigned int *SPIRXBUF  =   (unsigned int *)0x7047; /* SPI Serial receive buffer register*/
unsigned int *SPITXBUF  =   (unsigned int *)0x7048; /* SPI Serial transmit buffer register*/
unsigned int *SPIDAT        =   (unsigned int *)0x7049; /* SPI Serial data register*/
unsigned int *SPIPRI        =   (unsigned int *)0x704F; /* SPI Priority control register*/


/* SCI registers*/

unsigned int *SCICCR        =   (unsigned int *)0x7050; /* SCI Communication control register */
unsigned int *SCICTL1   =   (unsigned int *)0x7051; /* SCI Control register 1*/
unsigned int *SCIHBAUD  =   (unsigned int *)0x7052; /* SCI Baud Rate MS byte register */
unsigned int *SCILBAUD  =   (unsigned int *)0x7053; /* SCI Baud Rate LS byte register*/
unsigned int *SCICTL2   =   (unsigned int *)0x7054; /* SCI Control register 2*/
unsigned int *SCIRXST   =   (unsigned int *)0x7055; /* SCI Receiver Status register*/
unsigned int *SCIRXEMU  =   (unsigned int *)0x7056; /* SCI Emulation Data Buffer register */
unsigned int *SCIRXBUF  =   (unsigned int *)0x7057; /* SCI Receiver Data buffer register*/
unsigned int *SCITXBUF  =   (unsigned int *)0x7059; /* SCI Transmit Data buffer register*/
unsigned int *SCIPRI        =   (unsigned int *)0x705F; /* SCI Priority control register*/


/* Event Manager A (EVA) registers*/

unsigned int *GPTCONA   =   (unsigned int *)0x7400; /* GP Timer control register A*/
unsigned int *T1CNT         =   (unsigned int *)0x7401; /* GP Timer 1 counter register*/
unsigned int *T1CMPR        =   (unsigned int *)0x7402; /* GP Timer 1 compare register*/
unsigned int *T1PR      =   (unsigned int *)0x7403; /* GP Timer 1 period register*/
unsigned int *T1CON         =   (unsigned int *)0x7404; /* GP Timer 1 control register*/
unsigned int *T2CNT         =   (unsigned int *)0x7405; /* GP Timer 2 counter register*/
unsigned int *T2CMPR        =   (unsigned int *)0x7406; /* GP Timer 2 compare register*/
unsigned int *T2PR      =   (unsigned int *)0x7407; /* GP Timer 2 period register*/
unsigned int *T2CON         =   (unsigned int *)0x7408; /* GP Timer 2 control register*/

unsigned int *COMCONA   =   (unsigned int *)0x7411; /* Compare control register A */
unsigned int *ACTRA         =   (unsigned int *)0x7413; /* Full compare Action control register A*/
unsigned int *DBTCONA   =   (unsigned int *)0x7415; /* Dead朾and timer control register A */

unsigned int *CMPR1         =   (unsigned int *)0x7417; /* Full compare unit compare register1 */
unsigned int *CMPR2         =   (unsigned int *)0x7418; /* Full compare unit compare register2 */
unsigned int *CMPR3         =   (unsigned int *)0x7419; /* Full compare unit compare register3 */

unsigned int *CAPCONA   =   (unsigned int *)0x7420; /* Capture control register A*/
unsigned int *CAPFIFOA  =   (unsigned int *)0x7422; /* Capture FIFO status register A */

unsigned int *CAP1FIFO  =   (unsigned int *)0x7423; /* Capture Channel 1 FIFO Top*/
unsigned int *CAP2FIFO  =   (unsigned int *)0x7424; /* Capture Channel 2 FIFO Top*/
unsigned int *CAP3FIFO  =   (unsigned int *)0x7425; /* Capture Channel 3 FIFO Top*/

unsigned int *CAP1FBOT  =   (unsigned int *)0x7427; /* Bottom reg. of capture FIFO stack 1*/
unsigned int *CAP2FBOT  =   (unsigned int *)0x7428; /* Bottom reg. of capture FIFO stack 2*/
unsigned int *CAP3FBOT  =   (unsigned int *)0x7429; /* Bottom reg. of capture FIFO stack 3 */

unsigned int *EVAIMRA   =   (unsigned int *)0x742C; /* Group A Interrupt Mask Register */
unsigned int *EVAIMRB   =   (unsigned int *)0x742D; /* Group B Interrupt Mask Register */
unsigned int *EVAIMRC   =   (unsigned int *)0x742E; /* Group C Interrupt Mask Register */