lcd_clk.v

来自「LCD1602.rar」· Verilog 代码 · 共 32 行

/***************************************************************************************
**	Module Name:	LCD_CLK
**	Descriptions:	create lcd clk about 500HZ delay time 2ms
**	wave figure:___________|-|(1CLK)_____________2ms___________________
****************************************************************************************/
module LCD_CLK(CLK,Clk_Lcd);
input CLK;
output Clk_Lcd;

reg [15:0] Count_Lcd;			//create Clk_Lcd clk


/* Fclk = 24M, Clk_Lcd = 500HZ 	*/
parameter Dat_Lcd = 16'd48000;


/***************************************************************************************
**	Globle variable: Count_Lcd
**	Descriptions:	create Clk_Lcd
****************************************************************************************/
always @(posedge CLK)
begin
	if (Clk_Lcd)
		Count_Lcd <= 16'd0;
	else	
		Count_Lcd <= Count_Lcd + 1'b1;
end
assign Clk_Lcd = (Count_Lcd == Dat_Lcd);	//Count_Lcd == dat_Lcd


endmodule