lcd1602.fnsim.qmsg

LCD1602.rar

{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add1 " "Info: Instantiated megafunction \"lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|altshift:result_ext_latency_ffs lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux0 " "Info: Instantiated megafunction \"lpm_mux:Mux0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_cbc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_cbc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_cbc " "Info: Found entity 1: mux_cbc" {  } { { "db/mux_cbc.tdf" "" { Text "D:/My Document/FPGA/LCD1602/db/mux_cbc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux1\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux1 " "Info: Instantiated megafunction \"lpm_mux:Mux1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux2 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux2\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux2 " "Info: Instantiated megafunction \"lpm_mux:Mux2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux3 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux3\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux3 " "Info: Instantiated megafunction \"lpm_mux:Mux3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux4\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux4 " "Info: Instantiated megafunction \"lpm_mux:Mux4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}