lcd1602.fnsim.qmsg

LCD1602.rar

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 09 20:58:46 2009 " "Info: Processing started: Wed Dec 09 20:58:46 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LCD1602 -c LCD1602 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD1602 -c LCD1602 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD1602_Dirver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD1602_Dirver.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD1602 " "Info: Found entity 1: LCD1602" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "LCD1602 " "Info: Elaborating entity \"LCD1602\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "72 64 LCD1602_Dirver.v(90) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(90): truncated value with size 72 to match size of target (64)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "72 64 LCD1602_Dirver.v(91) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(91): truncated value with size 72 to match size of target (64)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 91 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(103) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(103): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(111) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(111): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(119) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(119): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(126) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(126): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(134) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(134): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(145) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(145): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 145 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(152) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(152): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 152 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 LCD1602_Dirver.v(165) " "Warning (10230): Verilog HDL assignment warning at LCD1602_Dirver.v(165): truncated value with size 32 to match size of target (4)" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "LCD_CLK_function/LCD_CLK.v 1 1 " "Warning: Using design file LCD_CLK_function/LCD_CLK.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_CLK " "Info: Found entity 1: LCD_CLK" {  } { { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_CLK LCD_CLK:circuit1 " "Info: Elaborating entity \"LCD_CLK\" for hierarchy \"LCD_CLK:circuit1\"" {  } { { "LCD1602_Dirver.v" "circuit1" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 60 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "23 " "Info: Inferred 23 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "LCD1602_Dirver.v" "Add0" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add1\"" {  } { { "LCD1602_Dirver.v" "Add1" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 163 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" {  } { { "LCD1602_Dirver.v" "Mux0" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" {  } { { "LCD1602_Dirver.v" "Mux1" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" {  } { { "LCD1602_Dirver.v" "Mux2" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" {  } { { "LCD1602_Dirver.v" "Mux3" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux4\"" {  } { { "LCD1602_Dirver.v" "Mux4" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux5\"" {  } { { "LCD1602_Dirver.v" "Mux5" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux6\"" {  } { { "LCD1602_Dirver.v" "Mux6" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux7\"" {  } { { "LCD1602_Dirver.v" "Mux7" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux8\"" {  } { { "LCD1602_Dirver.v" "Mux8" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux9\"" {  } { { "LCD1602_Dirver.v" "Mux9" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux10\"" {  } { { "LCD1602_Dirver.v" "Mux10" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux11\"" {  } { { "LCD1602_Dirver.v" "Mux11" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux12\"" {  } { { "LCD1602_Dirver.v" "Mux12" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux13\"" {  } { { "LCD1602_Dirver.v" "Mux13" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux14 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux14\"" {  } { { "LCD1602_Dirver.v" "Mux14" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux15 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux15\"" {  } { { "LCD1602_Dirver.v" "Mux15" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux16 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux16\"" {  } { { "LCD1602_Dirver.v" "Mux16" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux17 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux17\"" {  } { { "LCD1602_Dirver.v" "Mux17" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux18 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux18\"" {  } { { "LCD1602_Dirver.v" "Mux18" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux19 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux19\"" {  } { { "LCD1602_Dirver.v" "Mux19" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 97 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "LCD_CLK:circuit1\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"LCD_CLK:circuit1\|Add0\"" {  } { { "LCD_CLK_function/LCD_CLK.v" "Add0" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 27 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}