lcd1602.tan.qmsg

LCD1602.rar

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK E E_buf 9.682 ns register " "Info: tco from clock \"CLK\" to destination pin \"E\" through register \"E_buf\" is 9.682 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 184 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 184; CLK Node = 'CLK'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns E_buf 2 REG LC_X2_Y1_N0 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y1_N0; Fanout = 2; REG Node = 'E_buf'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK E_buf } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK E_buf } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} E_buf {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.958 ns + Longest register pin " "Info: + Longest register to pin delay is 5.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns E_buf 1 REG LC_X2_Y1_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N0; Fanout = 2; REG Node = 'E_buf'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { E_buf } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.511 ns) 1.503 ns E~1 2 COMB LC_X2_Y1_N4 1 " "Info: 2: + IC(0.992 ns) + CELL(0.511 ns) = 1.503 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'E~1'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.503 ns" { E_buf E~1 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.133 ns) + CELL(2.322 ns) 5.958 ns E 3 PIN PIN_3 0 " "Info: 3: + IC(2.133 ns) + CELL(2.322 ns) = 5.958 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'E'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { E~1 E } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.833 ns ( 47.55 % ) " "Info: Total cell delay = 2.833 ns ( 47.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.125 ns ( 52.45 % ) " "Info: Total interconnect delay = 3.125 ns ( 52.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.958 ns" { E_buf E~1 E } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.958 ns" { E_buf {} E~1 {} E {} } { 0.000ns 0.992ns 2.133ns } { 0.000ns 0.511ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK E_buf } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} E_buf {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.958 ns" { E_buf E~1 E } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.958 ns" { E_buf {} E~1 {} E {} } { 0.000ns 0.992ns 2.133ns } { 0.000ns 0.511ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "E_En RESET CLK -1.753 ns register " "Info: th for register \"E_En\" (data pin = \"RESET\", clock pin = \"CLK\") is -1.753 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 184 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 184; CLK Node = 'CLK'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns E_En 2 REG LC_X2_Y1_N3 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; REG Node = 'E_En'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK E_En } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK E_En } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} E_En {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.322 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns RESET 1 PIN PIN_28 155 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 155; PIN Node = 'RESET'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.129 ns) + CELL(1.061 ns) 5.322 ns E_En 2 REG LC_X2_Y1_N3 2 " "Info: 2: + IC(3.129 ns) + CELL(1.061 ns) = 5.322 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; REG Node = 'E_En'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.190 ns" { RESET E_En } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 41.21 % ) " "Info: Total cell delay = 2.193 ns ( 41.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.129 ns ( 58.79 % ) " "Info: Total interconnect delay = 3.129 ns ( 58.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { RESET E_En } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { RESET {} RESET~combout {} E_En {} } { 0.000ns 0.000ns 3.129ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK E_En } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} E_En {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { RESET E_En } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { RESET {} RESET~combout {} E_En {} } { 0.000ns 0.000ns 3.129ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Peak virtual memory: 131 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 09 21:18:45 2009 " "Info: Processing ended: Wed Dec 09 21:18:45 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}