lcd1602.tan.qmsg

LCD1602.rar

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } } { "f:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register LCD_CLK:circuit1\|Count_Lcd\[5\] register Address\[2\] 87.28 MHz 11.457 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 87.28 MHz between source register \"LCD_CLK:circuit1\|Count_Lcd\[5\]\" and destination register \"Address\[2\]\" (period= 11.457 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.748 ns + Longest register register " "Info: + Longest register to register delay is 10.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_CLK:circuit1\|Count_Lcd\[5\] 1 REG LC_X4_Y4_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N2; Fanout = 4; REG Node = 'LCD_CLK:circuit1\|Count_Lcd\[5\]'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_CLK:circuit1|Count_Lcd[5] } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.287 ns) + CELL(0.914 ns) 2.201 ns LCD_CLK:circuit1\|Equal0~0 2 COMB LC_X4_Y4_N5 1 " "Info: 2: + IC(1.287 ns) + CELL(0.914 ns) = 2.201 ns; Loc. = LC_X4_Y4_N5; Fanout = 1; COMB Node = 'LCD_CLK:circuit1\|Equal0~0'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.201 ns" { LCD_CLK:circuit1|Count_Lcd[5] LCD_CLK:circuit1|Equal0~0 } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.795 ns) + CELL(0.740 ns) 4.736 ns LCD_CLK:circuit1\|Equal0~4 3 COMB LC_X4_Y3_N6 18 " "Info: 3: + IC(1.795 ns) + CELL(0.740 ns) = 4.736 ns; Loc. = LC_X4_Y3_N6; Fanout = 18; COMB Node = 'LCD_CLK:circuit1\|Equal0~4'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { LCD_CLK:circuit1|Equal0~0 LCD_CLK:circuit1|Equal0~4 } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.241 ns Decoder0~0 4 COMB LC_X4_Y3_N7 4 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.241 ns; Loc. = LC_X4_Y3_N7; Fanout = 4; COMB Node = 'Decoder0~0'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LCD_CLK:circuit1|Equal0~4 Decoder0~0 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.210 ns) + CELL(0.200 ns) 7.651 ns Address\[7\]~16 5 COMB LC_X4_Y3_N5 8 " "Info: 5: + IC(2.210 ns) + CELL(0.200 ns) = 7.651 ns; Loc. = LC_X4_Y3_N5; Fanout = 8; COMB Node = 'Address\[7\]~16'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.410 ns" { Decoder0~0 Address[7]~16 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.854 ns) + CELL(1.243 ns) 10.748 ns Address\[2\] 6 REG LC_X5_Y1_N2 4 " "Info: 6: + IC(1.854 ns) + CELL(1.243 ns) = 10.748 ns; Loc. = LC_X5_Y1_N2; Fanout = 4; REG Node = 'Address\[2\]'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.097 ns" { Address[7]~16 Address[2] } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.297 ns ( 30.68 % ) " "Info: Total cell delay = 3.297 ns ( 30.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.451 ns ( 69.32 % ) " "Info: Total interconnect delay = 7.451 ns ( 69.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.748 ns" { LCD_CLK:circuit1|Count_Lcd[5] LCD_CLK:circuit1|Equal0~0 LCD_CLK:circuit1|Equal0~4 Decoder0~0 Address[7]~16 Address[2] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "10.748 ns" { LCD_CLK:circuit1|Count_Lcd[5] {} LCD_CLK:circuit1|Equal0~0 {} LCD_CLK:circuit1|Equal0~4 {} Decoder0~0 {} Address[7]~16 {} Address[2] {} } { 0.000ns 1.287ns 1.795ns 0.305ns 2.210ns 1.854ns } { 0.000ns 0.914ns 0.740ns 0.200ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 184 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 184; CLK Node = 'CLK'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns Address\[2\] 2 REG LC_X5_Y1_N2 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y1_N2; Fanout = 4; REG Node = 'Address\[2\]'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK Address[2] } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK Address[2] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} Address[2] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 184 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 184; CLK Node = 'CLK'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns LCD_CLK:circuit1\|Count_Lcd\[5\] 2 REG LC_X4_Y4_N2 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N2; Fanout = 4; REG Node = 'LCD_CLK:circuit1\|Count_Lcd\[5\]'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK LCD_CLK:circuit1|Count_Lcd[5] } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK LCD_CLK:circuit1|Count_Lcd[5] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} LCD_CLK:circuit1|Count_Lcd[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK Address[2] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} Address[2] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK LCD_CLK:circuit1|Count_Lcd[5] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} LCD_CLK:circuit1|Count_Lcd[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.748 ns" { LCD_CLK:circuit1|Count_Lcd[5] LCD_CLK:circuit1|Equal0~0 LCD_CLK:circuit1|Equal0~4 Decoder0~0 Address[7]~16 Address[2] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "10.748 ns" { LCD_CLK:circuit1|Count_Lcd[5] {} LCD_CLK:circuit1|Equal0~0 {} LCD_CLK:circuit1|Equal0~4 {} Decoder0~0 {} Address[7]~16 {} Address[2] {} } { 0.000ns 1.287ns 1.795ns 0.305ns 2.210ns 1.854ns } { 0.000ns 0.914ns 0.740ns 0.200ns 0.200ns 1.243ns } "" } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK Address[2] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} Address[2] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK LCD_CLK:circuit1|Count_Lcd[5] } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} LCD_CLK:circuit1|Count_Lcd[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "DB\[7\]~reg0 RESET CLK 4.095 ns register " "Info: tsu for register \"DB\[7\]~reg0\" (data pin = \"RESET\", clock pin = \"CLK\") is 4.095 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.110 ns + Longest pin register " "Info: + Longest pin to register delay is 7.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns RESET 1 PIN PIN_28 155 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 155; PIN Node = 'RESET'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.176 ns) + CELL(0.740 ns) 4.048 ns RS~3 2 COMB LC_X3_Y3_N2 9 " "Info: 2: + IC(2.176 ns) + CELL(0.740 ns) = 4.048 ns; Loc. = LC_X3_Y3_N2; Fanout = 9; COMB Node = 'RS~3'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.916 ns" { RESET RS~3 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.819 ns) + CELL(1.243 ns) 7.110 ns DB\[7\]~reg0 3 REG LC_X4_Y2_N2 1 " "Info: 3: + IC(1.819 ns) + CELL(1.243 ns) = 7.110 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; REG Node = 'DB\[7\]~reg0'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.062 ns" { RS~3 DB[7]~reg0 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.81 % ) " "Info: Total cell delay = 3.115 ns ( 43.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.995 ns ( 56.19 % ) " "Info: Total interconnect delay = 3.995 ns ( 56.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.110 ns" { RESET RS~3 DB[7]~reg0 } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.110 ns" { RESET {} RESET~combout {} RS~3 {} DB[7]~reg0 {} } { 0.000ns 0.000ns 2.176ns 1.819ns } { 0.000ns 1.132ns 0.740ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 184 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 184; CLK Node = 'CLK'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns DB\[7\]~reg0 2 REG LC_X4_Y2_N2 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; REG Node = 'DB\[7\]~reg0'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK DB[7]~reg0 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK DB[7]~reg0 } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} DB[7]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.110 ns" { RESET RS~3 DB[7]~reg0 } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.110 ns" { RESET {} RESET~combout {} RS~3 {} DB[7]~reg0 {} } { 0.000ns 0.000ns 2.176ns 1.819ns } { 0.000ns 1.132ns 0.740ns 1.243ns } "" } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK DB[7]~reg0 } "NODE_NAME" } } { "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} DB[7]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}