lcd1602.fit.qmsg

LCD1602.rar

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.196 ns register register " "Info: Estimated most critical path is register to register delay of 10.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_CLK:circuit1\|Count_Lcd\[1\] 1 REG LAB_X4_Y4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 4; REG Node = 'LCD_CLK:circuit1\|Count_Lcd\[1\]'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_CLK:circuit1|Count_Lcd[1] } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.787 ns) + CELL(0.740 ns) 2.527 ns LCD_CLK:circuit1\|Equal0~1 2 COMB LAB_X5_Y3 1 " "Info: 2: + IC(1.787 ns) + CELL(0.740 ns) = 2.527 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'LCD_CLK:circuit1\|Equal0~1'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.527 ns" { LCD_CLK:circuit1|Count_Lcd[1] LCD_CLK:circuit1|Equal0~1 } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.740 ns) 4.107 ns LCD_CLK:circuit1\|Equal0~4 3 COMB LAB_X4_Y3 18 " "Info: 3: + IC(0.840 ns) + CELL(0.740 ns) = 4.107 ns; Loc. = LAB_X4_Y3; Fanout = 18; COMB Node = 'LCD_CLK:circuit1\|Equal0~4'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.580 ns" { LCD_CLK:circuit1|Equal0~1 LCD_CLK:circuit1|Equal0~4 } "NODE_NAME" } } { "LCD_CLK_function/LCD_CLK.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 5.287 ns Decoder0~0 4 COMB LAB_X4_Y3 4 " "Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.287 ns; Loc. = LAB_X4_Y3; Fanout = 4; COMB Node = 'Decoder0~0'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LCD_CLK:circuit1|Equal0~4 Decoder0~0 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 6.467 ns Decoder0~2 5 COMB LAB_X4_Y3 87 " "Info: 5: + IC(0.669 ns) + CELL(0.511 ns) = 6.467 ns; Loc. = LAB_X4_Y3; Fanout = 87; COMB Node = 'Decoder0~2'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Decoder0~0 Decoder0~2 } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.486 ns) + CELL(1.243 ns) 10.196 ns Disp_CodeSecond\[122\] 6 REG LAB_X6_Y1 1 " "Info: 6: + IC(2.486 ns) + CELL(1.243 ns) = 10.196 ns; Loc. = LAB_X6_Y1; Fanout = 1; REG Node = 'Disp_CodeSecond\[122\]'" {  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.729 ns" { Decoder0~2 Disp_CodeSecond[122] } "NODE_NAME" } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.148 ns ( 40.68 % ) " "Info: Total cell delay = 4.148 ns ( 40.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.048 ns ( 59.32 % ) " "Info: Total interconnect delay = 6.048 ns ( 59.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.196 ns" { LCD_CLK:circuit1|Count_Lcd[1] LCD_CLK:circuit1|Equal0~1 LCD_CLK:circuit1|Equal0~4 Decoder0~0 Decoder0~2 Disp_CodeSecond[122] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 " "Info: Average interconnect usage is 10% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "10 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 10% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "R_W GND " "Info: Pin R_W has GND driving its datain port" {  } { { "f:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/90sp2/quartus/bin/pin_planner.ppl" { R_W } } } { "f:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "R_W" } } } } { "LCD1602_Dirver.v" "" { Text "D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v" 30 -1 0 } } { "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { R_W } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 40 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 40 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "182 " "Info: Peak virtual memory: 182 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 09 21:18:38 2009 " "Info: Processing ended: Wed Dec 09 21:18:38 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}