prev_cmp_lcd1602.sim.qmsg

LCD1602.rar

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 09 20:55:49 2009 " "Info: Processing started: Wed Dec 09 20:55:49 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off LCD1602 -c LCD1602 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off LCD1602 -c LCD1602" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "LCD_CLK_function/LCD1602.vwf " "Info: Using vector source file \"LCD_CLK_function/LCD1602.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "LCD1602.vwf LCD1602.sim_ori.vwf " "Info: A backup of LCD1602.vwf called LCD1602.sim_ori.vwf has been created in the db folder" {  } {  } 0 0 "A backup of %1!s! called %2!s! has been created in the db folder" 0 0 "" 0 -1}  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0 "" 0 -1}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[0\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[0\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[53\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[53\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[53\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[53\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[5\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[5\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[61\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[61\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[61\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[61\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[13\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[13\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[13\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[13\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[16\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[16\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[16\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[16\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[17\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[17\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[17\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[17\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[37\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[37\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[37\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[37\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[21\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[21\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[21\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[21\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[25\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[25\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[25\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[25\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[45\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[45\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[45\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[45\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[29\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[29\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[29\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[29\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeSecond\[32\] " "Info: Register: \|LCD1602\|Disp_CodeSecond\[32\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|LCD1602\|Disp_CodeFirst\[32\] " "Info: Register: \|LCD1602\|Disp_CodeFirst\[32\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Inverted registers were found during simulation" 0 0 "" 0 -1}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0 -1}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0 -1}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0 -1}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     26.01 % " "Info: Simulation coverage is      26.01 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0 -1}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "140951 " "Info: Number of transitions in simulation is 140951" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0 -1}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "LCD1602.vwf " "Info: Vector file LCD1602.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Peak virtual memory: 116 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 09 20:55:53 2009 " "Info: Processing ended: Wed Dec 09 20:55:53 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}