📄 lcd1602.fit.rpt
字号:
; 0 ; 0 ;
; 1 ; 8 ;
; 2 ; 3 ;
; 3 ; 4 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 6.63) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 8 ;
; 5 ; 2 ;
; 6 ; 3 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 2 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+------------------------------------------------------------+
; Estimated Delay Added for Hold Timing ;
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Dec 09 21:18:35 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LCD1602 -c LCD1602
Info: Selected device EPM240T100C5 for design "LCD1602"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM240T100A5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Device EPM570T100A5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 14
Info: Automatically promoted some destinations of signal "RESET" to use Global clock
Info: Destination "E_En" may be non-global or may not use global clock
Info: Destination "RS~3" may be non-global or may not use global clock
Info: Pin "RESET" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Extra Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00
Info: Finished register packing
Warning: Ignored locations or region assignments to the following nodes
Warning: Node "BEEP" is assigned to location or region, but does not exist in design
Warning: Node "COL[0]" is assigned to location or region, but does not exist in design
Warning: Node "COL[1]" is assigned to location or region, but does not exist in design
Warning: Node "COL[2]" is assigned to location or region, but does not exist in design
Warning: Node "COL[3]" is assigned to location or region, but does not exist in design
Warning: Node "CS[0]" is assigned to location or region, but does not exist in design
Warning: Node "CS[1]" is assigned to location or region, but does not exist in design
Warning: Node "DIG[0]" is assigned to location or region, but does not exist in design
Warning: Node "DIG[1]" is assigned to location or region, but does not exist in design
Warning: Node "DIG[2]" is assigned to location or region, but does not exist in design
Warning: Node "DIG[3]" is assigned to location or region, but does not exist in design
Warning: Node "DS18B20" is assigned to location or region, but does not exist in design
Warning: Node "LED[0]" is assigned to location or region, but does not exist in design
Warning: Node "LED[1]" is assigned to location or region, but does not exist in design
Warning: Node "LED[2]" is assigned to location or region, but does not exist in design
Warning: Node "LED[3]" is assigned to location or region, but does not exist in design
Warning: Node "LED[4]" is assigned to location or region, but does not exist in design
Warning: Node "LED[5]" is assigned to location or region, but does not exist in design
Warning: Node "LED[6]" is assigned to location or region, but does not exist in design
Warning: Node "LED[7]" is assigned to location or region, but does not exist in design
Warning: Node "PS2_CLK" is assigned to location or region, but does not exist in design
Warning: Node "PS2_DAT" is assigned to location or region, but does not exist in design
Warning: Node "ROW[0]" is assigned to location or region, but does not exist in design
Warning: Node "ROW[1]" is assigned to location or region, but does not exist in design
Warning: Node "ROW[2]" is assigned to location or region, but does not exist in design
Warning: Node "ROW[3]" is assigned to location or region, but does not exist in design
Warning: Node "RXD" is assigned to location or region, but does not exist in design
Warning: Node "SEG[0]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[1]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[2]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[3]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[4]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[5]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[6]" is assigned to location or region, but does not exist in design
Warning: Node "SEG[7]" is assigned to location or region, but does not exist in design
Warning: Node "TXD" is assigned to location or region, but does not exist in design
Warning: Node "_RET" is assigned to location or region, but does not exist in design
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 10.196 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 4; REG Node = 'LCD_CLK:circuit1|Count_Lcd[1]'
Info: 2: + IC(1.787 ns) + CELL(0.740 ns) = 2.527 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'LCD_CLK:circuit1|Equal0~1'
Info: 3: + IC(0.840 ns) + CELL(0.740 ns) = 4.107 ns; Loc. = LAB_X4_Y3; Fanout = 18; COMB Node = 'LCD_CLK:circuit1|Equal0~4'
Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.287 ns; Loc. = LAB_X4_Y3; Fanout = 4; COMB Node = 'Decoder0~0'
Info: 5: + IC(0.669 ns) + CELL(0.511 ns) = 6.467 ns; Loc. = LAB_X4_Y3; Fanout = 87; COMB Node = 'Decoder0~2'
Info: 6: + IC(2.486 ns) + CELL(1.243 ns) = 10.196 ns; Loc. = LAB_X6_Y1; Fanout = 1; REG Node = 'Disp_CodeSecond[122]'
Info: Total cell delay = 4.148 ns ( 40.68 % )
Info: Total interconnect delay = 6.048 ns ( 59.32 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 10% of the available device resources
Info: Peak interconnect usage is 10% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin R_W has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 40 warnings
Info: Peak virtual memory: 182 megabytes
Info: Processing ended: Wed Dec 09 21:18:38 2009
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02
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