📄 lcd1602.fit.rpt
字号:
Fitter report for LCD1602
Wed Dec 09 21:18:38 2009
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Pin-Out File
5. Fitter Resource Usage Summary
6. Input Pins
7. Output Pins
8. I/O Bank Usage
9. All Package Pins
10. Output Pin Default Load For Reported TCO
11. Fitter Resource Utilization by Entity
12. Delay Chain Summary
13. Control Signals
14. Global & Other Fast Signals
15. Non-Global High Fan-Out Signals
16. Interconnect Usage Summary
17. LAB Logic Elements
18. LAB-wide Signals
19. LAB Signals Sourced
20. LAB Signals Sourced Out
21. LAB Distinct Inputs
22. Fitter Device Options
23. Estimated Delay Added for Hold Timing
24. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+----------------------------------------------+
; Fitter Status ; Successful - Wed Dec 09 21:18:38 2009 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; LCD1602 ;
; Top-level Entity Name ; LCD1602 ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 214 / 240 ( 89 % ) ;
; Total pins ; 13 / 80 ( 16 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate full fit report during ECO compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/My Document/FPGA/LCD1602/LCD1602.pin.
+------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+--------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------+
; Total logic elements ; 214 / 240 ( 89 % ) ;
; -- Combinational with no register ; 30 ;
; -- Register only ; 93 ;
; -- Combinational with a register ; 91 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 24 ;
; -- 3 input functions ; 6 ;
; -- 2 input functions ; 39 ;
; -- 1 input functions ; 50 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 189 ;
; -- arithmetic mode ; 25 ;
; -- qfbk mode ; 7 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 79 ;
; -- asynchronous clear/load mode ; 153 ;
; ; ;
; Total registers ; 184 / 240 ( 77 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 28 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 13 / 80 ( 16 % ) ;
; -- Clock pins ; 1 / 4 ( 25 % ) ;
; Global signals ; 2 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 12% / 14% / 10% ;
; Peak interconnect usage (total/H/V) ; 12% / 14% / 10% ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 184 ;
; Highest non-global fan-out signal ; Decoder0~2 ;
; Highest non-global fan-out ; 87 ;
; Total fan-out ; 870 ;
; Average fan-out ; 3.83 ;
+---------------------------------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
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