📄 lcd1602.map.rpt
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Analysis & Synthesis report for LCD1602
Wed Dec 09 21:18:33 2009
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Registers Removed During Synthesis
8. Removed Registers Triggering Further Register Optimizations
9. General Register Statistics
10. Inverted Register Statistics
11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Parameter Settings for User Entity Instance: Top-level Entity: |LCD1602
13. Parameter Settings for User Entity Instance: LCD_CLK:circuit1
14. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Dec 09 21:18:33 2009 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; LCD1602 ;
; Top-level Entity Name ; LCD1602 ;
; Family ; MAX II ;
; Total logic elements ; 222 ;
; Total pins ; 13 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM240T100C5 ; ;
; Top-level entity name ; LCD1602 ; LCD1602 ;
; Family name ; MAX II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------+
; LCD_CLK_function/LCD_CLK.v ; yes ; User Verilog HDL File ; D:/My Document/FPGA/LCD1602/LCD_CLK_function/LCD_CLK.v ;
; LCD1602_Dirver.v ; yes ; User Verilog HDL File ; D:/My Document/FPGA/LCD1602/LCD1602_Dirver.v ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 222 ;
; -- Combinational with no register ; 38 ;
; -- Register only ; 101 ;
; -- Combinational with a register ; 83 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 24 ;
; -- 3 input functions ; 6 ;
; -- 2 input functions ; 39 ;
; -- 1 input functions ; 50 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 197 ;
; -- arithmetic mode ; 25 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 17 ;
; -- asynchronous clear/load mode ; 153 ;
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