lcd1602_dirver.v

LCD1602.rar

/**************************************************************************************
**	File Name: LCD1602_Dirver
**	top-level module:LCD1602_Dirver
**	Create By:	lixuechuan
**	Create Date:	2009-12-09
**	Last Veasions:	0.1v
**	Descriptions:	1. lcd1602 dirver program
					2.
**	IOsetting:	Tcl_MAX240T.tcl
**----------------------------------------------------------------------------------
**	Hard platform:	MAX240T100C experment board
**	Soft platform:	Runnint environment: Quartus II 9.0v
					Synsthesis environment:Quartus II 9.0v
					Simulation tools:	Quartus II 9.0V
**-----------------------------------------------------------------------------------
**	Modified Info:	
***************************************************************************************/



/************************************************************************************
**	Module Name:	LCD1602_Dirver
**	Descriptions:	

*************************************************************************************/
//module LCD1602_Dirver(CLK,Clk_Lcd,RS,R_W,E,DB);
module LCD1602(CLK,RESET,RS,R_W,E,DB);
input CLK,RESET;
output E;
output reg RS, R_W;
output reg [7:0] DB;

wire Clk_Lcd;
reg E_En;					//E clk enable,=1 enable, =0 disable
reg [3:0] Count_1M;
reg E_buf;					//LCD clk



reg[3:0] State;
parameter 	Disp_On = 8'h0f,	//all on
			Disp_Clear = 8'h01,
			Disp_AChome = 8'h02,
			Disp_Mode = 8'h06,	//AC auto add,picture static
			Disp_Function = 8'h38,/* D4= 1:8位数据接口,0:4位数据接口,D3=1:两行显示 0:一行显示 
									D2 = 1: 5*10点阵 0 :5*7点阵*/
			Disp_Ac = 8'h80;	//AC write (Disp_AC | ac)
			


reg [7:0] Address;			
reg [127:0] Disp_CodeFirst;
reg [127:0] Disp_CodeSecond;
parameter 	Disp_memory1 = "welcome to      ",
			Disp_memory2 = "www.donghuar.com";


/**********************************************************************************
**	Calling:module LCD_CLK(CLK,Clk_Lcd);
***********************************************************************************/
LCD_CLK circuit1 (CLK,Clk_Lcd);


assign E = (E_En)? E_buf : 1'b0;
/***********************************************************************************
**	Global variable: E_buf Count _1M 
**	Descriptions:	create the LCD clock 
**	Wave figure:	___________|---1us---|_________2ms___________|-------|______
************************************************************************************/
always @(posedge CLK)
begin
	if (Clk_Lcd)
	begin
		Count_1M <= 4'd0;		//start to count
		E_buf <= 1'b1;
	end
	
	else if (Count_1M == 4'd12)	E_buf <= 1'b0;	//stop
	
	else Count_1M <= Count_1M + 1'b1;
end

/***********************************************************************************
**	Global variable: E_En 
************************************************************************************/
always @(posedge CLK or negedge RESET)
begin
	if (!RESET)
	begin
		State <= 4'd0;
		Disp_CodeFirst <= Disp_memory1;
		Disp_CodeSecond <= Disp_memory2;
		Address <= 8'd0;
	end
	
	else if (Clk_Lcd)
	begin	//State <= State + 1'b1;
		case (State)
			4'd0: begin
				E_En <= 1'b1;	//flower 3 sentences in define do not more use LE
				RS <= 1'B0;
				R_W <= 1'B0;
				DB <= Disp_On;
				State <= State + 1'b1;
			end
			
			4'd1: begin
				E_En <= 1'b1;
				RS <= 1'B0;
				R_W <= 1'B0;
				DB <= Disp_Clear;
				State <= State + 1'b1;
			end
			
			4'd2: begin
				E_En <= 1'b1;
				RS <= 1'B0;
				R_W <= 1'B0;
				DB <= Disp_Mode;
				State <= State + 1'b1;
			end
			4'd3: begin
				E_En <= 1'b1;
				RS <= 1'B0;
				R_W <= 1'B0;
				DB <= Disp_Function;
				State <= State + 1'b1;
			end
			
			4'd4: begin
				E_En <= 1'b1;
				RS <= 1'B0;
				R_W <= 1'B0;
				DB <= Disp_AChome;
				State <= State + 1'b1;
			end			

			4'd5: begin
				E_En <= 1'b1;
				RS <= 1'B1;
				R_W <= 1'B0;
				DB <= Disp_CodeFirst[127:120];
				Disp_CodeFirst <= (Disp_CodeFirst << 4'd8);
				Address <= Address + 1'b1;
				if (Address == 8'd15)
					State <= State + 1'b1;
			end
			4'd6: begin
				E_En <= 1'b1;
				RS <= 1'B0;
				R_W <= 1'B0;
				DB <= Disp_Ac | 8'h40;	//second page
				State <= State + 1'b1;
				
				Address <= 8'd0;
			end
			
			4'd7: begin
				E_En <= 1'b1;
				RS <= 1'B1;
				R_W <= 1'B0;
				DB <= Disp_CodeSecond[127:120];
				Disp_CodeSecond <= (Disp_CodeSecond << 4'd8);
				Address <= Address + 1'b1;
				if (Address == 8'd15)
					State <= State + 1'b1;
			end
			
			default:begin State <= State; E_En <= 1'b0; end
		endcase
	end
end


endmodule

/***********************************END FILE*****************************************/