pre_prcs_top.v

基于FPGA的防火墙系统设计.rar

//remove isl vlan mpls header,caculate the packet lenth,remove short packet
//and long packet,drop short packet and long packet
//-----------------------------------------------------------------------------
// Title      : pre process top modlue
// Project    : 
//-----------------------------------------------------------------------------
// File       : pre_prcs_top.v
// Author     : 
// Date       : 07-10-25
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------
`timescale 1ns/10ps

module pre_prcs_top(
sys_clk,
rx_clk,
sys_rst_n,
rd_data_out,
rd_sof_n,
rd_eof_n,
rd_src_rdy_n,
rd_dst_rdy_n,
rx_fifo_status,
fc_sop_ih,
fc_eop_ih,
fc_vld_ih,
fc_dat_ih,
fc_mod_ih,
ih_pb_fc,
conf_wr_cal,      
conf_rd_cal,      
conf_clr_cal,     
conf_addr_cal,
conf_wdat_cal,
cal_rdat_conf
);

parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//Global Signals
input             sys_clk;
input             sys_rst_n;

input             rx_clk;

//interface with the mac core
input  [7:0]        rd_data_out;
input               rd_sof_n;
input               rd_eof_n;
input               rd_src_rdy_n;
output              rd_dst_rdy_n;
input  [3:0]        rx_fifo_status;

//interface with key_gen
output              fc_sop_ih;
output              fc_eop_ih;
output              fc_vld_ih;
output    [31:0]    fc_dat_ih;
output    [1:0]     fc_mod_ih;
input               ih_pb_fc;

input               conf_wr_cal;      
input               conf_rd_cal;      
input               conf_clr_cal;     
input     [3:0]     conf_addr_cal;
input     [15:0]    conf_wdat_cal;
output    [15:0]    cal_rdat_conf;
/*-------------------------------------------------------------------*\
                            wire Description
\*-------------------------------------------------------------------*/ 

wire          rd_dst_rdy_n;
wire          rmv_sop_cal;
wire          rmv_eop_cal;
wire          rmv_vld_cal;
wire          rmv_err_cal;
wire  [31:0]  rmv_dat_cal;
wire  [1:0]   rmv_mod_cal;
wire          cal_afull_rmv;

wire          cal_sop_fc;
wire          cal_eop_fc;
wire  [31:0]  cal_dat_fc;
wire  [1:0]   cal_mod_fc;
wire          cal_vld_fc;
wire          cal_spkt_fc;
wire          cal_lpkt_fc;
wire          cal_epkt_fc;
wire          fc_afull_cal;

wire  [15:0]  cal_rdat_conf;

wire          fc_sop_ih;
wire          fc_eop_ih;
wire          fc_vld_ih;
wire  [31:0]  fc_dat_ih;
wire  [1:0]   fc_mod_ih;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/
hd_rmv u_hd_rmv(
    .sys_clk            (sys_clk),
    .rx_clk             (rx_clk),
    .sys_rst_n          (sys_rst_n),
    .rd_data_out        (rd_data_out[7:0]),   
    .rd_sof_n           (rd_sof_n),  
    .rd_eof_n           (rd_eof_n),
    .rd_src_rdy_n       (rd_src_rdy_n),  
    .rd_dst_rdy_n       (rd_dst_rdy_n), 
    .rx_fifo_status     (rx_fifo_status[3:0]),
    
    .rmv_sop_cal        (rmv_sop_cal),  
    .rmv_eop_cal        (rmv_eop_cal),  
    .rmv_vld_cal        (rmv_vld_cal),  
    .rmv_err_cal        (rmv_err_cal),  
    .rmv_dat_cal        (rmv_dat_cal[31:0]),  
    .rmv_mod_cal        (rmv_mod_cal[1:0]),  
    .cal_afull_rmv      (cal_afull_rmv)
   );

len_cal u_len_cal(
    .sys_clk            (sys_clk),
    .sys_rst_n          (sys_rst_n),
    .rmv_sop_cal        (rmv_sop_cal),
    .rmv_eop_cal        (rmv_eop_cal),
    .rmv_vld_cal        (rmv_vld_cal),
    .rmv_err_cal        (rmv_err_cal),
    .rmv_dat_cal        (rmv_dat_cal[31:0]),
    .rmv_mod_cal        (rmv_mod_cal[1:0]),
    .cal_afull_rmv      (cal_afull_rmv),

    .cal_sop_fc         (cal_sop_fc),
    .cal_eop_fc         (cal_eop_fc),
    .cal_dat_fc         (cal_dat_fc[31:0]),
    .cal_mod_fc         (cal_mod_fc[1:0]),
    .cal_vld_fc         (cal_vld_fc), 
    .cal_spkt_fc        (cal_spkt_fc), 
    .cal_lpkt_fc        (cal_lpkt_fc), 
    .cal_epkt_fc        (cal_epkt_fc),  
    .fc_afull_cal       (fc_afull_cal),
    
    .conf_wr_cal        (conf_wr_cal),
    .conf_rd_cal        (conf_rd_cal),
    .conf_clr_cal       (conf_clr_cal),
    .conf_addr_cal      (conf_addr_cal[3:0]),
    .conf_wdat_cal      (conf_wdat_cal[15:0]),
    .cal_rdat_conf      (cal_rdat_conf[15:0])
);

fc u_fc(
    .sys_clk            (sys_clk), 
    .sys_rst_n          (sys_rst_n),
    .cal_sop_fc         (cal_sop_fc), 
    .cal_eop_fc         (cal_eop_fc), 
    .cal_dat_fc         (cal_dat_fc[31:0]),
    .cal_mod_fc         (cal_mod_fc[1:0]), 
    .cal_vld_fc         (cal_vld_fc), 
    .cal_spkt_fc        (cal_spkt_fc), 
    .cal_lpkt_fc        (cal_lpkt_fc),
    .cal_epkt_fc        (cal_epkt_fc),
    .fc_afull_cal       (fc_afull_cal),

    .fc_sop_ih          (fc_sop_ih), 
    .fc_eop_ih          (fc_eop_ih), 
    .fc_vld_ih          (fc_vld_ih), 
    .fc_dat_ih          (fc_dat_ih[31:0]), 
    .fc_mod_ih          (fc_mod_ih[1:0]),  
    .ih_pb_fc           (ih_pb_fc)
);

endmodule