📄 tri_mode_eth_mac_v3_2.xco
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# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = FalseSET verilogsim = TrueSET workingdirectory = C:\my_projec\firewallSET speedgrade = -7SET simulationfiles = StructuralSET asysymbol = TrueSET addpads = FalseSET device = xc2vp30SET implementationfiletype = ngcSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff896SET createndf = FalseSET designentry = VerilogSET devicefamily = virtex2pSET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Tri_Mode_Ethernet_MAC family Xilinx,_Inc. 3.2# END Select# BEGIN ParametersCSET number_of_address_table_entries=0CSET management_interface=falseCSET component_name=tri_mode_eth_mac_v3_2CSET physical_interface=GMIICSET address_filter=falseCSET clock_enables=true# END ParametersGENERATE
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