rx_client_fifo.v

基于FPGA的防火墙系统设计.rar

//-----------------------------------------------------------------------------
// Title      : Client to Local-link Receiver FIFO
// Project    : Tri-Mode Ethernet MAC
//-----------------------------------------------------------------------------
// File       : rx_client_fifo.v
// Author     : Xilinx
//-----------------------------------------------------------------------------
// Copyright (c) 2004-2005 by Xilinx, Inc. All rights reserved.
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is distributed under license
// from Xilinx, Inc., and may be used, copied and/or
// disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you
// a license to use this text/file solely for design, simulation,
// implementation and creation of design files limited
// to Xilinx devices or technologies. Use with non-Xilinx
// devices or technologies is expressly prohibited and
// immediately terminates your license unless covered by
// a separate agreement.
//
// Xilinx is providing this design, code, or information
// "as is" solely for use in developing programs and
// solutions for Xilinx devices. By providing this design,
// code, or information as one possible implementation of
// this feature, application or standard, Xilinx is making no
// representation that this implementation is free from any
// claims of infringement. You are responsible for
// obtaining any rights you may require for your implementation.
// Xilinx expressly disclaims any warranty whatsoever with
// respect to the adequacy of the implementation, including
// but not limited to any warranties or representations that this
// implementation is free from claims of infringement, implied
// warranties of merchantability or fitness for a particular
// purpose.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications are
// expressly prohibited.
//
// This copyright and support notice must be retained as part
// of this text at all times. (c) Copyright 2004-2005 Xilinx, Inc.
// All rights reserved.
//------------------------------------------------------------------------
// Description: This is the receiver side local link fifo for the client 
//              loopback design of the Tri-Mode Ethernet MAC core
//
//              The FIFO is created from 2 Block RAMs of size 2048
//              words of 9-bits per word, giving a total frame memory capacity
//              of 4096 bytes.
//
//              Frame data received from the MAC receiver is written into the
//              FIFO on the rx_clk: both registered versions of rx_data[7:0]
//              and rx_data_valid are stored.
//
//              The rx_good_frame and rx_bad_frame signals are used to
//              qualify the frame.  A frame for which rx_bad_frame was
//              asserted will cause the FIFO write address pointer to be
//              reset to the base address of that frame.  In this way
//              the bad frame will be overwritten with the next received
//              frame and is therefore dropped from the FIFO.
//
//              When there is at least one complete frame in the FIFO,
//              the 8 bit Local-link read interface will be enabled allowing
//              data to be read from the fifo.
//
//              The FIFO memory size can be increased by expanding the tx_addr
//              and write_addr signal widths, to address further BRAMs.
//              Control signals can be modified as commented in the FIFO
//              architecture.  Look for ** comments.
//-----------------------------------------------------------------------------


`timescale 1ps / 1ps

module rx_client_fifo
     (
        // MAC Interface
        rx_clk,
        rx_reset,
        rx_enable,
        rx_data,
        rx_data_valid,
        rx_good_frame,
        rx_bad_frame,
        overflow,
     
        // Local-link Interface
        read_clock_in,
        ll_reset, 
        data_out,
        rem_out,
        sof_out_n,
        eof_out_n,
        src_rdy_out_n,
        dst_rdy_in_n,
        fifo_status_out
     );

  //-----------------------------------------------------------------------------
  // Define Interface Signals
  //-----------------------------------------------------------------------------
  //MAC Interface
   input        rx_clk;
   input        rx_reset;
   input        rx_enable;
   input  [7:0] rx_data;
   input 	  rx_data_valid;
   input 	  rx_good_frame;
   input 	  rx_bad_frame;
   output 	  overflow;
     
  // Local-link Interface
   input 	  read_clock_in;
   input 	  ll_reset;
   output [7:0] data_out;
   output [0:0] rem_out;
   output 	  sof_out_n;
   output 	  eof_out_n;
   output 	  src_rdy_out_n;
   input 	  dst_rdy_in_n;
   output [3:0] fifo_status_out;

   
  //-----------------------------------------------------------------------------
  // Define Internal Signals
  //-----------------------------------------------------------------------------
  // Local link side data signals.
   reg        eof_out_n_int;
   reg        sof_out_n_int;
   reg        src_rdy_out_n_int;
   wire [7:0] read_data_int;
   wire [7:0] read_data_int_l;
   wire [7:0] read_data_int_u;
   wire       read_data_valid_int;
   reg  [7:0] read_data_pipe [0:1];
   reg  [0:1] read_data_valid_pipe;
   wire [0:0] read_dv_dv_l;
   wire [0:0] read_dv_dv_u;
  
  // Local link side control signals
   wire       read_addr_enable;
   wire       read_addr_enable_int;
   reg        read_addr_enable_reg;
   wire       read_addr_enable_reg_int;
   wire       read_mem_enable_u;
   wire       read_mem_enable_l;
   reg        frame_in_progress;
   wire       queue;
   reg        frame_transmitted;
   reg        ll_frame_received;
   reg  [2:0] ll_frame_received_toggle;
   wire       read_pipe_enable;
   reg        sending_frame;
   reg        sending_frame_reg;
   wire       frame_transmitted_pulse;
   reg        frame_transmitted_reg;
  
  // Client side data signals
   reg  [7:0] rx_data_reg;
   reg        rx_data_valid_reg;
   reg        rx_data_valid_reg_reg;
   reg        rx_good_frame_reg;
   reg        rx_bad_frame_reg;
   wire [0:0] rx_dv_dv;

   // Client side control signals.
   wire       rx_addr_enable;
   reg        frame_received_toggle;
   wire       rx_mem_enable;
   wire       rx_mem_enable_l;
   wire       rx_mem_enable_u;
  
  // Fifo Status signals
   wire       frame_in_fifo;
   reg        frame_in_fifo_held;
   reg        overflow_int_held;
   reg  [8:0] frame_count;
   wire [11:0] fifo_status_full;
   wire       full_pulse;
  
  // Local link side address signals
   wire [11:0] read_addr;
   reg [11:0] read_addr_int;
   reg [11:0] read_addr_reg;
   reg [11:0] read_addr_gray;
   reg [11:0] ll_rx_addr_bin;
   reg [11:0] ll_rx_addr_gray;
  
  // Client side address signals
   wire [11:0] rx_addr;
   reg [11:0] rx_addr_int;
   reg [11:0] rx_addr_reg;
   reg [11:0] rx_addr_sub;
   reg [11:0] start_addr;
   reg [11:0] rx_read_addr_gray;
   reg [11:0] rx_read_addr_bin;
   reg [11:0] rx_addr_gray;


   wire       GND;
   wire       VCC;
   wire [7:0] GND_BUS;

   // ASYNC_REG attributes added to simulate actual behaviour under
   // asynchronous operating conditions.
   //  synthesis attribute ASYNC_REG of rx_read_addr_gray        is "TRUE";
   //  synthesis attribute ASYNC_REG of ll_rx_addr_gray          is "TRUE";
   //  synthesis attribute ASYNC_REG of ll_frame_received_toggle is "TRUE";

   //  synthesis attribute KEEP of queue               is "TRUE";
   //  synthesis attribute KEEP of read_data_valid_int is "TRUE";
   //  synthesis attribute KEEP of frame_in_fifo       is "TRUE";

  // Small delay for simulation purposes.
//  constant dly : time := 1 ps;

   
  assign GND     = 1'b0;
  assign VCC     = 1'b1;
  assign GND_BUS = 8'b00000000;
   

  //---------------------------------------------------------------------------
  // Register the input signals from the receiver side of the MAC.
  //---------------------------------------------------------------------------
  always @(posedge rx_clk)
  begin
    if (rx_reset == 1'b1)
      begin
      rx_data_reg           <= 8'h00;
      rx_data_valid_reg     <= 1'b0;
      rx_good_frame_reg     <= 1'b0;
      rx_bad_frame_reg      <= 1'b0;
      end
    else if (rx_enable == 1'b1)
      begin
      rx_data_reg           <= rx_data;
      rx_data_valid_reg     <= rx_data_valid;
      rx_good_frame_reg     <= rx_good_frame;
      rx_bad_frame_reg      <= rx_bad_frame;
      end
  end

  // Register the data valid signal once more
  always @(posedge rx_clk)
  begin
    if (rx_reset == 1'b1)
      rx_data_valid_reg_reg <= 1'b0;
    else if (rx_enable == 1'b1)
      rx_data_valid_reg_reg <= rx_data_valid_reg;
  end

  //--------------------------------------------------------------------
  // The RAMB16_S9_S9 primitive defines the parity inputs and outputs 
  // as signals of type std_logic_vector(0 downto 0). These are 
  // connected to single bit std_logic signals in the FIFO. The 
  // following line converts between the different types.
  //--------------------------------------------------------------------
  assign rx_dv_dv[0] = rx_data_valid_reg;

  //--------------------------------------------------------------------
  // The write enable is asserted when the FIFO is receiving valid data
  // or storing delimiter byte.  Data is written either into the upper or lower
  // Block RAM depending on the upper bit of the write address.
  // **If the FIFO is expanded to use more BRAM, create rx_mem_enable signals
  // to address each BRAM using rx_addr[max:11]**
  //--------------------------------------------------------------------
  assign rx_mem_enable   = (rx_data_valid_reg | rx_data_valid_reg_reg) & rx_enable;
  assign rx_mem_enable_l =  rx_mem_enable & !(rx_addr[11]);
  assign rx_mem_enable_u =  rx_mem_enable & rx_addr[11];
  
  //---------------------------------------------------------------------------
  // Now write the registered data and data_valid signals into the memory
  // on the rx clock. Starting and stopping the address will control the flow
  // of data into the memory.
  //
  // **If the FIFO is expanded to use more BRAM, instantiate as below.
  // To control the rx side, create a rx_mem_enable signal for each BRAM as
  // above, data inputs and the rx_addr[10:0] are common to all BRAMs.
  // To control the read side, create a read_mem_enable signal for each BRAM as
  // below, and create read_data_int and read_dv_dv signals for each BRAM.  Mux
  // data outputs as shown below.  The read_addr[10:0] is common to all BRAMs.**
  //--------------------------------------------------------------------------- 
  // Block Ram for lower address space (rx_addr(11) = '0')
  RAMB16_S9_S9 ramgen_l
    (
      .WEA   (rx_mem_enable_l),
      .ENA   (rx_enable),
      .SSRA  (rx_reset),
      .CLKA  (rx_clk),
      .ADDRA (rx_addr[10:0]),
      .DIA   (rx_data_reg),
      .DIPA  (rx_dv_dv),
      .WEB   (GND),
      .ENB   (read_mem_enable_l),
      .SSRB  (ll_reset),
      .CLKB  (read_clock_in),
      .ADDRB (read_addr[10:0]),
      .DIB   (GND_BUS[7:0]),
      .DIPB  (GND_BUS[0:0]),
      .DOB   (read_data_int_l),
      .DOPB  (read_dv_dv_l));