system_incl.make

基于FPGA的防火墙系统设计.rar

#################################################################
# Makefile generated by Xilinx Platform Studio 
# Project:C:\myproj2\firewall\myxps\system.xmp
#################################################################

XILINX_EDK_DIR = g:/EDK

SYSTEM = system

MHSFILE = system.mhs

MSSFILE = system.mss

FPGA_ARCH = virtex2p

DEVICE = xc2vp30ff896-7

LANGUAGE = verilog

SEARCHPATHOPT =  -lp C:/V2P_CD/V2P_CD/lib/lib_rev_1_1/lib/

SUBMODULE_OPT =  -toplevel no -ti system_i

PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT)

LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT)

VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT)

TESTAPP_MEMORY_OUTPUT_DIR = TestApp_Memory
TESTAPP_MEMORY_OUTPUT = $(TESTAPP_MEMORY_OUTPUT_DIR)/executable.elf

TESTAPP_PERIPHERAL_OUTPUT_DIR = TestApp_Peripheral
TESTAPP_PERIPHERAL_OUTPUT = $(TESTAPP_PERIPHERAL_OUTPUT_DIR)/executable.elf

MYSOFTPROJ_OUTPUT_DIR = mysoftproj
MYSOFTPROJ_OUTPUT = $(MYSOFTPROJ_OUTPUT_DIR)/executable.elf

MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
BOOTLOOP_DIR = bootloops

PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf

BRAMINIT_ELF_FILES =  $(MYSOFTPROJ_OUTPUT) 
BRAMINIT_ELF_FILE_ARGS =   -pe ppc405_0 $(MYSOFTPROJ_OUTPUT) 

ALL_USER_ELF_FILES = $(TESTAPP_MEMORY_OUTPUT) $(TESTAPP_PERIPHERAL_OUTPUT) $(MYSOFTPROJ_OUTPUT) 

SIM_CMD = vsim

BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do

STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do

TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do

DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)

MIX_LANG_SIM_OPT = -mixed yes

SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT)  -s mti


LIBRARIES =  \
       ppc405_0/lib/libxil.a 
VPEXEC = virtualplatform/vpexec.exe

LIBSCLEAN_TARGETS = ppc405_0_libsclean 

PROGRAMCLEAN_TARGETS = TestApp_Memory_programclean TestApp_Peripheral_programclean mysoftproj_programclean 

CORE_STATE_DEVELOPMENT_FILES = g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\proc_common_pkg.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\family.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_muxcy.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_gate.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter_bit.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\inferred_lut4.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl_fifo2.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_bit.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_top.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter_top.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder_bit.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_dpram_select.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl16_fifo.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pselect.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\valid_be.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ld_arith_reg.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\mux_onehot.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\down_counter.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_pkg.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_steer.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\direct_path_cntr_ai.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a\hdl\vhdl\interrupt_control.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\pf_dly1_mux.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\ipif_control_wr.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_dp_cntl.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_top.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\ipif_control_rd.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_dp_cntl.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_top.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\reset_mir.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\brst_addr_cntr.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\opb_flex_addr_cntr.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\brst_addr_cntr_reg.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\opb_be_gen.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\srl_fifo3.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\write_buffer.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\opb_bam.vhd \
g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_c\hdl\vhdl\opb_ipif.vhd \
C:\myproj2\firewall\myxps\pcores\myfirewall_v1_00_a\hdl\verilog\user_logic.v \
C:\myproj2\firewall\myxps\pcores\myfirewall_v1_00_a\hdl\vhdl\myfirewall.vhd

WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \
implementation/reset_block_wrapper.ngc \
implementation/plb_wrapper.ngc \
implementation/opb_wrapper.ngc \
implementation/plb2opb_wrapper.ngc \
implementation/rs232_uart_1_wrapper.ngc \
implementation/leds_4bit_wrapper.ngc \
implementation/dipsws_4bit_wrapper.ngc \
implementation/pushbuttons_5bit_wrapper.ngc \
implementation/ps2_ports_wrapper.ngc \
implementation/plb_bram_if_cntlr_1_wrapper.ngc \
implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc \
implementation/ps2_ports_io_adapter_wrapper.ngc \
implementation/dcm_0_wrapper.ngc \
implementation/myfirewall_0_wrapper.ngc

POSTSYN_NETLIST = implementation/$(SYSTEM).ngc

SYSTEM_BIT = implementation/$(SYSTEM).bit

DOWNLOAD_BIT = implementation/download.bit

SYSTEM_ACE = implementation/$(SYSTEM).ace

UCF_FILE = data/system.ucf

BMM_FILE = implementation/$(SYSTEM).bmm

BITGEN_UT_FILE = etc/bitgen.ut

XFLOW_OPT_FILE = etc/fast_runtime.opt
XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)

XPLORER_DEPENDENCY = __xps/xplorer.opt
XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7

FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY)

#################################################################
# SOFTWARE APPLICATION TESTAPP_MEMORY
#################################################################

TESTAPP_MEMORY_SOURCES = TestApp_Memory/src/TestApp_Memory.c 

TESTAPP_MEMORY_HEADERS = 

TESTAPP_MEMORY_CC = powerpc-eabi-gcc
TESTAPP_MEMORY_CC_SIZE = powerpc-eabi-size
TESTAPP_MEMORY_CC_OPT = -O2
TESTAPP_MEMORY_CFLAGS = 
TESTAPP_MEMORY_CC_SEARCH = # -B
TESTAPP_MEMORY_LIBPATH = -L./ppc405_0/lib/ # -L
TESTAPP_MEMORY_INCLUDES = -I./ppc405_0/include/ # -I
TESTAPP_MEMORY_LFLAGS = # -l
TESTAPP_MEMORY_LINKER_SCRIPT = TestApp_Memory/src/TestApp_Memory_LinkScr.ld
TESTAPP_MEMORY_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(TESTAPP_MEMORY_LINKER_SCRIPT) 
TESTAPP_MEMORY_CC_DEBUG_FLAG =  -g 
TESTAPP_MEMORY_CC_PROFILE_FLAG = # -pg
TESTAPP_MEMORY_CC_GLOBPTR_FLAG= # -msdata=eabi
TESTAPP_MEMORY_CC_START_ADDR_FLAG=  #  # -Wl,-defsym -Wl,_START_ADDR=
TESTAPP_MEMORY_CC_STACK_SIZE_FLAG=  #  # -Wl,-defsym -Wl,_STACK_SIZE=
TESTAPP_MEMORY_CC_HEAP_SIZE_FLAG=  #  # -Wl,-defsym -Wl,_HEAP_SIZE=
TESTAPP_MEMORY_OTHER_CC_FLAGS= $(TESTAPP_MEMORY_CC_GLOBPTR_FLAG)  \
                  $(TESTAPP_MEMORY_CC_START_ADDR_FLAG) $(TESTAPP_MEMORY_CC_STACK_SIZE_FLAG) $(TESTAPP_MEMORY_CC_HEAP_SIZE_FLAG)  \
                  $(TESTAPP_MEMORY_LINKER_SCRIPT_FLAG) $(TESTAPP_MEMORY_CC_DEBUG_FLAG) $(TESTAPP_MEMORY_CC_PROFILE_FLAG) 

#################################################################
# SOFTWARE APPLICATION TESTAPP_PERIPHERAL
#################################################################

TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xgpio_tapp_example.c 

TESTAPP_PERIPHERAL_HEADERS = TestApp_Peripheral/src/gpio_header.h 

TESTAPP_PERIPHERAL_CC = powerpc-eabi-gcc
TESTAPP_PERIPHERAL_CC_SIZE = powerpc-eabi-size
TESTAPP_PERIPHERAL_CC_OPT = -O2
TESTAPP_PERIPHERAL_CFLAGS = 
TESTAPP_PERIPHERAL_CC_SEARCH = # -B
TESTAPP_PERIPHERAL_LIBPATH = -L./ppc405_0/lib/ # -L
TESTAPP_PERIPHERAL_INCLUDES = -I./ppc405_0/include/  -ITestApp_Peripheral/src/ # -I
TESTAPP_PERIPHERAL_LFLAGS = # -l
TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld
TESTAPP_PERIPHERAL_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(TESTAPP_PERIPHERAL_LINKER_SCRIPT) 
TESTAPP_PERIPHERAL_CC_DEBUG_FLAG =  -g 
TESTAPP_PERIPHERAL_CC_PROFILE_FLAG = # -pg
TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -msdata=eabi
TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG=  #  # -Wl,-defsym -Wl,_START_ADDR=
TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG=  #  # -Wl,-defsym -Wl,_STACK_SIZE=
TESTAPP_PERIPHERAL_CC_HEAP_SIZE_FLAG=  #  # -Wl,-defsym -Wl,_HEAP_SIZE=
TESTAPP_PERIPHERAL_OTHER_CC_FLAGS= $(TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG)  \
                  $(TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG) $(TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG) $(TESTAPP_PERIPHERAL_CC_HEAP_SIZE_FLAG)  \
                  $(TESTAPP_PERIPHERAL_LINKER_SCRIPT_FLAG) $(TESTAPP_PERIPHERAL_CC_DEBUG_FLAG) $(TESTAPP_PERIPHERAL_CC_PROFILE_FLAG) 

#################################################################
# SOFTWARE APPLICATION MYSOFTPROJ
#################################################################

MYSOFTPROJ_SOURCES = mysoftproj/Key_Read_In.c mysoftproj/myfirewall.c mysoftproj/MyFirewallProj.c 

MYSOFTPROJ_HEADERS = mysoftproj/myfirewall.h mysoftproj/myfirewall_reg.h 

MYSOFTPROJ_CC = powerpc-eabi-gcc
MYSOFTPROJ_CC_SIZE = powerpc-eabi-size
MYSOFTPROJ_CC_OPT = -O2
MYSOFTPROJ_CFLAGS = 
MYSOFTPROJ_CC_SEARCH = # -B
MYSOFTPROJ_LIBPATH = -L./ppc405_0/lib/ # -L
MYSOFTPROJ_INCLUDES = -I./ppc405_0/include/  -Imysoftproj/ # -I
MYSOFTPROJ_LFLAGS = # -l
MYSOFTPROJ_LINKER_SCRIPT = 
MYSOFTPROJ_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(MYSOFTPROJ_LINKER_SCRIPT) 
MYSOFTPROJ_CC_DEBUG_FLAG =  -g 
MYSOFTPROJ_CC_PROFILE_FLAG = # -pg
MYSOFTPROJ_CC_GLOBPTR_FLAG= # -msdata=eabi
MYSOFTPROJ_CC_START_ADDR_FLAG=  # -Wl,-defsym -Wl,_START_ADDR=
MYSOFTPROJ_CC_STACK_SIZE_FLAG=  # -Wl,-defsym -Wl,_STACK_SIZE=
MYSOFTPROJ_CC_HEAP_SIZE_FLAG=  # -Wl,-defsym -Wl,_HEAP_SIZE=
MYSOFTPROJ_OTHER_CC_FLAGS= $(MYSOFTPROJ_CC_GLOBPTR_FLAG)  \
                  $(MYSOFTPROJ_CC_START_ADDR_FLAG) $(MYSOFTPROJ_CC_STACK_SIZE_FLAG) $(MYSOFTPROJ_CC_HEAP_SIZE_FLAG)  \
                  $(MYSOFTPROJ_LINKER_SCRIPT_FLAG) $(MYSOFTPROJ_CC_DEBUG_FLAG) $(MYSOFTPROJ_CC_PROFILE_FLAG)