ps2_ports_io_adapter_wrapper_xst.srp

基于FPGA的防火墙系统设计.rar

Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "ps2_ports_io_adapter_wrapper_xst.prj"
Verilog Include Directory          : {"C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\dual_ps2_ioadapter_v1_00_a\hdl\verilog\" }

---- Target Parameters
Target Device                      : xc2vp30ff896-7
Output File Name                   : "../implementation/ps2_ports_io_adapter_wrapper.ngc"

---- Source Options
Top Module Name                    : ps2_ports_io_adapter_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\dual_ps2_ioadapter_v1_00_a/hdl/verilog/dual_ps2_ioadapter.v" in library dual_ps2_ioadapter_v1_00_a
Module <dual_ps2_ioadapter> compiled
Compiling verilog file "../hdl/ps2_ports_io_adapter_wrapper.v" in library work
Module <ps2_ports_io_adapter_wrapper> compiled
No errors in compilation
Analysis of file <"ps2_ports_io_adapter_wrapper_xst.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <ps2_ports_io_adapter_wrapper> in library <work>.

Analyzing hierarchy for module <dual_ps2_ioadapter> in library <dual_ps2_ioadapter_v1_00_a>.

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <ps2_ports_io_adapter_wrapper>.
Module <ps2_ports_io_adapter_wrapper> is correct for synthesis.
 
    Set user-defined property "X_CORE_INFO =  dual_ps2_ioadapter_v1_00_a" for unit <ps2_ports_io_adapter_wrapper>.
Analyzing module <dual_ps2_ioadapter> in library <dual_ps2_ioadapter_v1_00_a>.
Module <dual_ps2_ioadapter> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <dual_ps2_ioadapter>.
    Related source file is "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\dual_ps2_ioadapter_v1_00_a/hdl/verilog/dual_ps2_ioadapter.v".
Unit <dual_ps2_ioadapter> synthesized.


Synthesizing Unit <ps2_ports_io_adapter_wrapper>.
    Related source file is "../hdl/ps2_ports_io_adapter_wrapper.v".
Unit <ps2_ports_io_adapter_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ps2_ports_io_adapter_wrapper> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/ps2_ports_io_adapter_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 20

Cell Usage :
# BELS                             : 5
#      GND                         : 1
#      INV                         : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                       2  out of  13696     0%  
 Number of 4 input LUTs:                 4  out of  27392     0%  
 Number of IOs:                         20
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.275ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay:               0.275ns (Levels of Logic = 1)
  Source:            ps2_clk_tx_2 (PAD)
  Destination:       ps2_keyb_clk_T (PAD)

  Data Path: ps2_clk_tx_2 to ps2_keyb_clk_T
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     INV:I->O              0   0.275   0.000  ps2_ports_io_adapter/ps2_keyb_clk_T1_INV_0 (ps2_keyb_clk_T)
    ----------------------------------------
    Total                      0.275ns (0.275ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 32.02 / 32.36 s | Elapsed : 32.00 / 33.00 s
 
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Total memory usage is 182080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)