myfirewall_0_wrapper_xst.srp

基于FPGA的防火墙系统设计.rar

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 174
 Flip-Flops                                            : 174

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/myfirewall_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 155

Cell Usage :
# BELS                             : 192
#      GND                         : 1
#      INV                         : 4
#      LUT2                        : 56
#      LUT2_D                      : 2
#      LUT2_L                      : 30
#      LUT3                        : 18
#      LUT3_D                      : 3
#      LUT3_L                      : 2
#      LUT4                        : 62
#      LUT4_D                      : 2
#      LUT4_L                      : 3
#      MUXCY                       : 8
#      MUXF5                       : 1
# FlipFlops/Latches                : 174
#      FD                          : 45
#      FDC                         : 40
#      FDP                         : 4
#      FDR                         : 37
#      FDRE                        : 48
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                     142  out of  13696     1%  
 Number of Slice Flip Flops:           174  out of  27392     0%  
 Number of 4 input LUTs:               182  out of  27392     0%  
 Number of IOs:                        155
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+--------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                      | Load  |
-----------------------------------+--------------------------------------------+-------+
OPB_Clk                            | NONE(myfirewall_0/USER_LOGIC_I/slv_reg1_10)| 130   |
sys_clk_in_100m                    | NONE(myfirewall_0/USER_LOGIC_I/slv_reg3_0) | 44    |
-----------------------------------+--------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-------------------------------------------------------------------------------------------+-------------------------------------------+-------+
Control Signal                                                                             | Buffer(FF name)                           | Load  |
-------------------------------------------------------------------------------------------+-------------------------------------------+-------+
myfirewall_0/USER_LOGIC_I/sys_rst_in_inv(myfirewall_0/USER_LOGIC_I/sys_rst_in_inv1_INV_0:O)| NONE(myfirewall_0/USER_LOGIC_I/slv_reg3_0)| 44    |
-------------------------------------------------------------------------------------------+-------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 6.034ns (Maximum Frequency: 165.717MHz)
   Minimum input arrival time before clock: 2.361ns
   Maximum output required time after clock: 1.178ns
   Maximum combinational path delay: 0.373ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'OPB_Clk'
  Clock period: 6.034ns (frequency: 165.717MHz)
  Total number of paths / destination ports: 11374 / 170
-------------------------------------------------------------------------
Delay:               6.034ns (Levels of Logic = 7)
  Source:            myfirewall_0/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_0 (FF)
  Destination:       myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31 (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: myfirewall_0/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_0 to myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              7   0.370   0.601  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_0 (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_0)
     LUT3:I0->O            1   0.275   0.000  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/_and00102 (N1130)
     MUXF5:I0->O           2   0.303   0.396  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/_and0010_f5 (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/new_pw_s0)
     LUT4:I2->O            4   0.275   0.413  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/_and0001 (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/Bus2IP_CS)
     MUXCY:CI->O          25   0.415   0.797  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/PER_AR_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I/XST_WA.GEN_DECODE[0].MUXCY_I (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/Bus2IP_CE<1>)
     LUT3_D:I0->O         15   0.275   0.641  myfirewall_0/USER_LOGIC_I/slv_ip2bus_data<0>21 (myfirewall_0/USER_LOGIC_I/slv_ip2bus_data<0>_map9)
     LUT4:I2->O            2   0.275   0.514  myfirewall_0/USER_LOGIC_I/slv_ip2bus_data<14>66 (myfirewall_0/uIP2Bus_Data<14>)
     LUT2:I0->O            1   0.275   0.000  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/I_MIRROR/Rd_Data_Out<30>1 (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s1<30>)
     FDR:D                     0.208          myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_30
    ----------------------------------------
    Total                      6.034ns (2.672ns logic, 3.363ns route)
                                       (44.3% logic, 55.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
  Total number of paths / destination ports: 141 / 125
-------------------------------------------------------------------------
Offset:              2.361ns (Levels of Logic = 2)
  Source:            OPB_Rst (PAD)
  Destination:       myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31 (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_Rst to myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I0->O            1   0.275   0.467  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/_or00001_SW0 (N1125)
     LUT4:I0->O           32   0.275   0.671  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/_or00001 (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/_or0000)
     FDR:R                     0.536          myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31
    ----------------------------------------
    Total                      2.361ns (1.222ns logic, 1.139ns route)
                                       (51.8% logic, 48.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in_100m'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              0.208ns (Levels of Logic = 0)
  Source:            conf_rdat_ppc<15> (PAD)
  Destination:       myfirewall_0/USER_LOGIC_I/slv_reg3_15 (FF)
  Destination Clock: sys_clk_in_100m rising

  Data Path: conf_rdat_ppc<15> to myfirewall_0/USER_LOGIC_I/slv_reg3_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:D                     0.208          myfirewall_0/USER_LOGIC_I/slv_reg3_15
    ----------------------------------------
    Total                      0.208ns (0.208ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in_100m'
  Total number of paths / destination ports: 28 / 28
-------------------------------------------------------------------------
Offset:              0.370ns (Levels of Logic = 0)
  Source:            myfirewall_0/USER_LOGIC_I/ppc_we_n_conf (FF)
  Destination:       ppc_we_n_conf (PAD)
  Source Clock:      sys_clk_in_100m rising

  Data Path: myfirewall_0/USER_LOGIC_I/ppc_we_n_conf to ppc_we_n_conf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              0   0.370   0.000  myfirewall_0/USER_LOGIC_I/ppc_we_n_conf (ppc_we_n_conf)
    ----------------------------------------
    Total                      0.370ns (0.370ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
  Total number of paths / destination ports: 33 / 33
-------------------------------------------------------------------------
Offset:              1.178ns (Levels of Logic = 1)
  Source:            myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2 (FF)
  Destination:       Sl_xferAck (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2 to Sl_xferAck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.370   0.533  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2 (myfirewall_0/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2)
     LUT2:I0->O            0   0.275   0.000  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/Sln_xferAck1 (Sl_xferAck)
    ----------------------------------------
    Total                      1.178ns (0.645ns logic, 0.533ns route)
                                       (54.8% logic, 45.2% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               0.373ns (Levels of Logic = 1)
  Source:            OPB_select (PAD)
  Destination:       Sl_xferAck (PAD)

  Data Path: OPB_select to Sl_xferAck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I1->O            0   0.275   0.000  myfirewall_0/OPB_IPIF_I/OPB_BAM_I/Sln_xferAck1 (Sl_xferAck)
    ----------------------------------------
    Total                      0.373ns (0.373ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 87.11 / 87.39 s | Elapsed : 87.00 / 88.00 s
 
--> 

Total memory usage is 233848 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  171 (   0 filtered)
Number of infos    :    8 (   0 filtered)