myfirewall_0_wrapper_xst.srp

基于FPGA的防火墙系统设计.rar

	C_OPB_DWIDTH = 32
	C_PIPELINE_MODEL = 5
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.

Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.
	C_AB = 16
	C_AW = 32
	C_BAR = "01000000011100000000000000000000"

Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.
	C_AB = 0
	C_AW = 16
	C_BAR = "0000000000000000"

Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "00"

Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "01"

Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "10"

Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "11"

Analyzing hierarchy for entity <IPIF_Steer> in library <proc_common_v2_00_a> (architecture <IMP>) with generics.
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_SMALLEST = 16

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <myfirewall_0_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "X_CORE_INFO =  myfirewall_v1_00_a" for unit <myfirewall_0_wrapper>.
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:37 - Unknown property "SIGIS".
Entity <myfirewall_0_wrapper> analyzed. Unit <myfirewall_0_wrapper> generated.

Analyzing generic Entity <myfirewall> in library <myfirewall_v1_00_a> (Architecture <IMP>).
	C_HIGHADDR = "01000000011100001111111111111111"
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_BASEADDR = "01000000011100000000000000000000"
	C_FAMILY = "virtex2p"
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'Bus2IP_CS' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'Bus2IP_CE' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'Bus2IP_AddrValid' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'Bus2IP_RNW' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'Bus2IP_Burst' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'RFIFO2IP_AlmostFull' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'RFIFO2IP_Full' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'RFIFO2IP_Vacancy' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'RFIFO2IP_WrAck' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'WFIFO2IP_AlmostEmpty' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'WFIFO2IP_Empty' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'WFIFO2IP_Occupancy' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'WFIFO2IP_RdAck' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'IP2INTC_Irpt' of component 'opb_ipif'.
WARNING:Xst:753 - "C:/myproj2/firewall/myxps/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd" line 354: Unconnected output port 'Bus2IP_Freeze' of component 'opb_ipif'.
Entity <myfirewall> analyzed. Unit <myfirewall> generated.

Analyzing generic Entity <opb_ipif> in library <opb_ipif_v3_01_c> (Architecture <imp>).
	C_ARD_ID_ARRAY = (100)
	C_ARD_NUM_CE_ARRAY = (4)
	C_ARD_DWIDTH_ARRAY = (16)
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000011100000000000000000000",
	                          "0000000000000000000000000000000001000000011100001111111111111111")
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0))
	C_DEV_BURST_ENABLE = 0
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
	C_INCLUDE_WR_BUF = 0
	C_FAMILY = "virtex2p"
	C_INCLUDE_ADDR_CNTR = 0
	C_OPB_AWIDTH = 32
	C_IP_INTR_MODE_ARRAY = (0)
	C_OPB_DWIDTH = 32
	C_PIPELINE_MODEL = 5
Entity <opb_ipif> analyzed. Unit <opb_ipif> generated.

Analyzing generic Entity <opb_bam> in library <opb_ipif_v3_01_c> (Architecture <implementation>).
	C_IP_INTR_MODE_ARRAY = (0)
	C_INCLUDE_WR_BUF = 0
	C_ARD_ID_ARRAY = (100)
	C_PIPELINE_MODEL = 5
	C_OPB_DWIDTH = 32
	C_OPB_AWIDTH = 32
	C_ARD_NUM_CE_ARRAY = (4)
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000011100000000000000000000",
	                          "0000000000000000000000000000000001000000011100001111111111111111")
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0))
	C_ARD_DWIDTH_ARRAY = (16)
	C_DEV_MIR_ENABLE = 0
	C_DEV_BLK_ID = 0
	C_DEV_BURST_ENABLE = 0
	C_INCLUDE_ADDR_CNTR = 0
	C_FAMILY = "virtex2p"
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" line 2314: Unconnected output port 'Rd_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" line 2314: Unconnected output port 'BE_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" line 2340: Unconnected output port 'Wr_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" line 2340: Unconnected output port 'Rd_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" line 2363: Unconnected output port 'Wr_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" line 2363: Unconnected output port 'BE_Out' of component 'IPIF_Steer'.
INFO:Xst:1304 - Contents of register <opb_seqaddr_s0> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <opb_seqaddr_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <opb_seqaddr_s0_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <last_burstrd_xferack_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <bus2ip_burst_s1_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <last_burstrd_xferack_d2> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
Entity <opb_bam> analyzed. Unit <opb_bam> generated.

Analyzing generic Entity <pselect.1> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_AW = 32
	C_BAR = "01000000011100000000000000000000"
	C_AB = 16
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.1> analyzed. Unit <pselect.1> generated.

Analyzing generic Entity <pselect.2> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_AB = 0
	C_AW = 16
	C_BAR = "0000000000000000"
Entity <pselect.2> analyzed. Unit <pselect.2> generated.

Analyzing generic Entity <pselect.3> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_AB = 2
	C_AW = 2
	C_BAR = "00"
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.3> analyzed. Unit <pselect.3> generated.

Analyzing generic Entity <pselect.4> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_AW = 2
	C_BAR = "01"
	C_AB = 2
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.4> analyzed. Unit <pselect.4> generated.

Analyzing generic Entity <pselect.5> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_BAR = "10"
	C_AW = 2
	C_AB = 2
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.5> analyzed. Unit <pselect.5> generated.

Analyzing generic Entity <pselect.6> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_BAR = "11"
	C_AW = 2
	C_AB = 2
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.6> analyzed. Unit <pselect.6> generated.

Analyzing generic Entity <IPIF_Steer> in library <proc_common_v2_00_a> (Architecture <IMP>).
	C_DWIDTH = 32
	C_SMALLEST = 16
	C_AWIDTH = 32
Entity <IPIF_Steer> analyzed. Unit <IPIF_Steer> generated.

Analyzing module <user_logic> in library <myfirewall_v1_00_a>.
	C_AWIDTH = 32'sb00000000000000000000000000100000
	C_DWIDTH = 32'sb00000000000000000000000000010000
	C_NUM_CE = 32'sb00000000000000000000000000000100
Module <user_logic> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:1304 - Contents of register <byte_index> in unit <user_logic> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <user_logic>.
    Related source file is "C:\myproj2\firewall\myxps\pcores\myfirewall_v1_00_a/hdl/verilog/user_logic.v".
WARNING:Xst:647 - Input <Bus2IP_Addr> is never used.
WARNING:Xst:1872 - Variable <bit_index> is used but never assigned.
WARNING:Xst:1872 - Variable <byte_index> is used but never assigned.
    Found 8-bit register for signal <ppc_addr_conf>.
    Found 1-bit register for signal <ppc_we_n_conf>.
    Found 1-bit register for signal <ppc_clr_n_conf>.
    Found 1-bit register for signal <ppc_re_n_conf>.
    Found 16-bit register for signal <ppc_wdat_conf>.
    Found 1-bit register for signal <ppc_ce_n_conf>.
    Found 16-bit register for signal <slv_reg0>.
    Found 16-bit register for signal <slv_reg1>.
    Found 16-bit register for signal <slv_reg2>.
    Found 16-bit register for signal <slv_reg3>.
    Summary:
	inferred  92 D-type flip-flop(s).
Unit <user_logic> synthesized.


Synthesizing Unit <pselect_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A> is never used.
WARNING:Xst:1780 - Signal <lut_out> is never used or assigned.
Unit <pselect_2> synthesized.


Synthesizing Unit <IPIF_Steer>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd".
WARNING:Xst:647 - Input <Addr<0:29>> is never used.
WARNING:Xst:647 - Input <Addr<31>> is never used.
    Found 16-bit 4-to-1 multiplexer for signal <Rd_Data_Out<16:31>>.
    Found 4-bit 4-to-1 multiplexer for signal <BE_Out>.
    Summary:
	inferred  20 Multiplexer(s).
Unit <IPIF_Steer> synthesized.


Synthesizing Unit <pselect_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A<16:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<4>> is never used or assigned.
Unit <pselect_1> synthesized.


Synthesizing Unit <pselect_3>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".