opb_wrapper_xst.srp

基于FPGA的防火墙系统设计.rar

Synthesizing Unit <opb_arbiter>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/opb_arbiter.vhd".
Unit <opb_arbiter> synthesized.


Synthesizing Unit <opb_v20>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/opb_v20.vhd".
WARNING:Xst:647 - Input <Sl_DBusEn> is never used.
WARNING:Xst:647 - Input <Sl_DBusEn32_63> is never used.
WARNING:Xst:647 - Input <M_DBusEn32_63<0>> is never used.
WARNING:Xst:647 - Input <M_DBusEn<0>> is never used.
WARNING:Xst:646 - Signal <arb_errack> is assigned but never used.
WARNING:Xst:646 - Signal <arb_dbus> is assigned but never used.
WARNING:Xst:646 - Signal <arb_toutsup> is assigned but never used.
WARNING:Xst:646 - Signal <arb_retry> is assigned but never used.
WARNING:Xst:646 - Signal <arb_xferack> is assigned but never used.
Unit <opb_v20> synthesized.


Synthesizing Unit <opb_wrapper>.
    Related source file is "C:/myproj2/firewall/myxps/hdl/opb_wrapper.vhd".
Unit <opb_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 1
 1-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 2
 Flip-Flops                                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <opb_wrapper> ...

Optimizing unit <opb_v20> ...

Optimizing unit <or_gate_6> ...

Optimizing unit <or_gate_4> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 6
 Flip-Flops                                            : 6

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/opb_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 488

Cell Usage :
# BELS                             : 124
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 33
#      LUT3                        : 42
#      LUT3_L                      : 1
#      LUT4                        : 45
#      VCC                         : 1
# FlipFlops/Latches                : 6
#      FDR                         : 1
#      FDRE                        : 4
#      FDS                         : 1
# Shift Registers                  : 1
#      SRL16                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                      71  out of  13696     0%  
 Number of Slice Flip Flops:             6  out of  27392     0%  
 Number of 4 input LUTs:               123  out of  27392     0%  
    Number used as logic:              122
    Number used as Shift registers:      1
 Number of IOs:                        488
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+--------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                    | Load  |
-----------------------------------+--------------------------------------------------------------------------+-------+
OPB_Clk                            | NONE(opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_3)| 7     |
-----------------------------------+--------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 2.928ns (Maximum Frequency: 341.530MHz)
   Minimum input arrival time before clock: 3.750ns
   Maximum output required time after clock: 0.370ns
   Maximum combinational path delay: 1.760ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'OPB_Clk'
  Clock period: 2.928ns (frequency: 341.530MHz)
  Total number of paths / destination ports: 20 / 10
-------------------------------------------------------------------------
Delay:               2.928ns (Levels of Logic = 0)
  Source:            opb/POR_SRL_I (FF)
  Destination:       opb/POR_FF_I (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: opb/POR_SRL_I to opb/POR_FF_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16:CLK->Q          1   2.720   0.000  opb/POR_SRL_I (opb/srl_time_out)
     FDS:D                     0.208          opb/POR_FF_I
    ----------------------------------------
    Total                      2.928ns (2.928ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
  Total number of paths / destination ports: 98 / 10
-------------------------------------------------------------------------
Offset:              3.750ns (Levels of Logic = 5)
  Source:            Sl_retry<2> (PAD)
  Destination:       opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (FF)
  Destination Clock: OPB_Clk rising

  Data Path: Sl_retry<2> to opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            1   0.275   0.369  opb/ARBITER_HAS_NO_PROC_INTF.OPB_retry_I/_or0000_SW0 (N40)
     LUT4:I3->O            2   0.275   0.514  opb/ARBITER_HAS_NO_PROC_INTF.OPB_retry_I/_or0000 (OPB_retry)
     LUT4:I0->O            1   0.275   0.349  opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_or00017 (opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_or0001_map3)
     LUT3_L:I2->LO         1   0.275   0.138  opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_or000130_SW0 (N146)
     LUT4:I3->O            1   0.275   0.331  opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_or000130 (opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_or0001)
     FDR:R                     0.536          opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout
    ----------------------------------------
    Total                      3.750ns (2.047ns logic, 1.703ns route)
                                       (54.6% logic, 45.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              0.370ns (Levels of Logic = 0)
  Source:            opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (FF)
  Destination:       OPB_timeout (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout to OPB_timeout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              0   0.370   0.000  opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (OPB_timeout)
    ----------------------------------------
    Total                      0.370ns (0.370ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 541 / 149
-------------------------------------------------------------------------
Delay:               1.760ns (Levels of Logic = 3)
  Source:            Sl_DBus<160> (PAD)
  Destination:       OPB_DBus<0> (PAD)

  Data Path: Sl_DBus<160> to OPB_DBus<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            1   0.275   0.370  opb/ARBITER_HAS_NO_PROC_INTF.OPB_rdDBus_I/_or0030_SW0 (N112)
     LUT4:I3->O            1   0.275   0.429  opb/ARBITER_HAS_NO_PROC_INTF.OPB_rdDBus_I/_or0030 (OPB_rdDBus<0>)
     LUT2:I1->O            0   0.275   0.000  opb/OPB_DBus_I/_or00301 (OPB_DBus<0>)
    ----------------------------------------
    Total                      1.760ns (0.961ns logic, 0.799ns route)
                                       (54.6% logic, 45.4% route)

=========================================================================
CPU : 33.28 / 33.44 s | Elapsed : 34.00 / 34.00 s
 
--> 

Total memory usage is 237560 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   42 (   0 filtered)
Number of infos    :    1 (   0 filtered)