opb_wrapper_xst.srp

基于FPGA的防火墙系统设计.rar

Entity <opb_arbiter> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/opb_v20.vhd" in Library opb_v20_v1_10_c.
Entity <opb_v20> compiled.
Entity <opb_v20> (Architecture <imp>) compiled.
Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/opb_wrapper.vhd" in Library work.
Entity <opb_wrapper> compiled.
Entity <opb_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <opb_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <opb_v20> in library <opb_v20_v1_10_c> (architecture <imp>) with generics.
	C_BASEADDR = "11111111111111111111111111111111"
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
	C_DYNAM_PRIORITY = 0
	C_EXT_RESET_HIGH = 1
	C_HIGHADDR = "00000000000000000000000000000000"
	C_NUM_MASTERS = 1
	C_NUM_SLAVES = 6
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_PARK = 0
	C_PROC_INTRFCE = 0
	C_REG_GRANTS = 1
	C_USE_LUT_OR = 1

Analyzing hierarchy for entity <or_gate> in library <opb_arbiter_v1_02_e> (architecture <imp>) with generics.
	C_USE_LUT_OR = true
	C_BUS_WIDTH = 32
	C_OR_WIDTH = 1

Analyzing hierarchy for entity <or_gate> in library <opb_arbiter_v1_02_e> (architecture <imp>) with generics.
	C_USE_LUT_OR = true
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 4

Analyzing hierarchy for entity <or_gate> in library <opb_arbiter_v1_02_e> (architecture <imp>) with generics.
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = true

Analyzing hierarchy for entity <or_gate> in library <opb_arbiter_v1_02_e> (architecture <imp>) with generics.
	C_BUS_WIDTH = 32
	C_OR_WIDTH = 2
	C_USE_LUT_OR = true

Analyzing hierarchy for entity <or_gate> in library <opb_arbiter_v1_02_e> (architecture <imp>) with generics.
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 6
	C_USE_LUT_OR = true

Analyzing hierarchy for entity <or_gate> in library <opb_arbiter_v1_02_e> (architecture <imp>) with generics.
	C_BUS_WIDTH = 32
	C_OR_WIDTH = 6
	C_USE_LUT_OR = true

Analyzing hierarchy for entity <opb_arbiter> in library <opb_arbiter_v1_02_e> (architecture <implementation>) with generics.
	C_BASEADDR = "11111111111111111111111111111111"
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
	C_DYNAM_PRIORITY = 0
	C_HIGHADDR = "00000000000000000000000000000000"
	C_NUM_MASTERS = 1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_PARK = 0
	C_PROC_INTRFCE = 0
	C_REG_GRANTS = 1

Analyzing hierarchy for entity <opb_arbiter_core> in library <opb_arbiter_v1_02_e> (architecture <implementation>) with generics.
	C_DEV_MIR_ENABLE = 0
	C_DYNAM_PRIORITY = false
	C_NUM_MASTERS = 1
	C_DEV_BLK_ID = 0
	C_BASEADDR = "11111111111111111111111111111111"
	C_HIGHADDR = "00000000000000000000000000000000"
	C_OPBADDR_WIDTH = 32
	C_OPBDATA_WIDTH = 32
	C_PARK = false
	C_PROC_INTRFCE = false
	C_REG_GRANTS = true

Analyzing hierarchy for entity <watchdog_timer> in library <opb_arbiter_v1_02_e> (architecture <implementation>).

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <opb_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "X_CORE_INFO =  opb_v20_v1_10_c" for unit <opb_wrapper>.
Entity <opb_wrapper> analyzed. Unit <opb_wrapper> generated.

Analyzing generic Entity <opb_v20> in library <opb_v20_v1_10_c> (Architecture <imp>).
	C_OPB_DWIDTH = 32
	C_PROC_INTRFCE = 0
	C_PARK = 0
	C_OPB_AWIDTH = 32
	C_DEV_MIR_ENABLE = 0
	C_DYNAM_PRIORITY = 0
	C_DEV_BLK_ID = 0
	C_BASEADDR = "11111111111111111111111111111111"
	C_NUM_SLAVES = 6
	C_EXT_RESET_HIGH = 1
	C_HIGHADDR = "00000000000000000000000000000000"
	C_NUM_MASTERS = 1
	C_USE_LUT_OR = 1
	C_REG_GRANTS = 1
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/opb_v20.vhd" line 485: Instantiating black box module <SRL16>.
    Set user-defined property "INIT =  FFFF" for instance <POR_SRL_I> in unit <opb_v20>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/opb_v20.vhd" line 499: Instantiating black box module <FDS>.
Entity <opb_v20> analyzed. Unit <opb_v20> generated.

Analyzing generic Entity <or_gate.1> in library <opb_arbiter_v1_02_e> (Architecture <imp>).
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true
	C_BUS_WIDTH = 32
Entity <or_gate.1> analyzed. Unit <or_gate.1> generated.

Analyzing generic Entity <or_gate.2> in library <opb_arbiter_v1_02_e> (Architecture <imp>).
	C_BUS_WIDTH = 4
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true
Entity <or_gate.2> analyzed. Unit <or_gate.2> generated.

Analyzing generic Entity <or_gate.3> in library <opb_arbiter_v1_02_e> (Architecture <imp>).
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = true
Entity <or_gate.3> analyzed. Unit <or_gate.3> generated.

Analyzing generic Entity <or_gate.4> in library <opb_arbiter_v1_02_e> (Architecture <imp>).
	C_OR_WIDTH = 2
	C_USE_LUT_OR = true
	C_BUS_WIDTH = 32
Entity <or_gate.4> analyzed. Unit <or_gate.4> generated.

Analyzing generic Entity <or_gate.5> in library <opb_arbiter_v1_02_e> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 6
	C_USE_LUT_OR = true
Entity <or_gate.5> analyzed. Unit <or_gate.5> generated.

Analyzing generic Entity <or_gate.6> in library <opb_arbiter_v1_02_e> (Architecture <imp>).
	C_USE_LUT_OR = true
	C_OR_WIDTH = 6
	C_BUS_WIDTH = 32
Entity <or_gate.6> analyzed. Unit <or_gate.6> generated.

Analyzing generic Entity <opb_arbiter> in library <opb_arbiter_v1_02_e> (Architecture <implementation>).
	C_BASEADDR = "11111111111111111111111111111111"
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
	C_DYNAM_PRIORITY = 0
	C_HIGHADDR = "00000000000000000000000000000000"
	C_NUM_MASTERS = 1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_PARK = 0
	C_PROC_INTRFCE = 0
	C_REG_GRANTS = 1
Entity <opb_arbiter> analyzed. Unit <opb_arbiter> generated.

Analyzing generic Entity <opb_arbiter_core> in library <opb_arbiter_v1_02_e> (Architecture <implementation>).
	C_BASEADDR = "11111111111111111111111111111111"
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
	C_DYNAM_PRIORITY = false
	C_HIGHADDR = "00000000000000000000000000000000"
	C_NUM_MASTERS = 1
	C_OPBADDR_WIDTH = 32
	C_OPBDATA_WIDTH = 32
	C_PARK = false
	C_PROC_INTRFCE = false
	C_REG_GRANTS = true
Entity <opb_arbiter_core> analyzed. Unit <opb_arbiter_core> generated.

Analyzing Entity <watchdog_timer> in library <opb_arbiter_v1_02_e> (Architecture <implementation>).
Entity <watchdog_timer> analyzed. Unit <watchdog_timer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <or_gate_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_1> synthesized.


Synthesizing Unit <or_gate_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_2> synthesized.


Synthesizing Unit <or_gate_3>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_3> synthesized.


Synthesizing Unit <or_gate_4>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_4> synthesized.


Synthesizing Unit <or_gate_5>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_5> synthesized.


Synthesizing Unit <or_gate_6>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_6> synthesized.


Synthesizing Unit <watchdog_timer>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/watchdog_timer.vhd".
    Found 1-bit register for signal <OPB_timeout>.
    Found 4-bit up counter for signal <timeout_cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <watchdog_timer> synthesized.


Synthesizing Unit <opb_arbiter_core>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/opb_arbiter_core.vhd".
WARNING:Xst:647 - Input <M_request<0>> is never used.
WARNING:Xst:647 - Input <OPB_BE> is never used.
WARNING:Xst:647 - Input <OPB_RNW> is never used.
WARNING:Xst:647 - Input <OPB_buslock> is never used.
WARNING:Xst:647 - Input <OPB_Dbus> is never used.
WARNING:Xst:647 - Input <OPB_Abus> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
WARNING:Xst:1780 - Signal <priority_register> is never used or assigned.
WARNING:Xst:1780 - Signal <bus_park> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_data> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_reg_rdce> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_reg_wrce> is never used or assigned.
WARNING:Xst:1780 - Signal <arb2bus_data> is never used or assigned.
WARNING:Xst:1780 - Signal <arb2bus_rdack> is never used or assigned.
WARNING:Xst:1780 - Signal <mgrant_n> is never used or assigned.
WARNING:Xst:1780 - Signal <mgrant> is never used or assigned.
WARNING:Xst:1780 - Signal <any_mgrant> is never used or assigned.
WARNING:Xst:1780 - Signal <arb_cycle> is never used or assigned.
WARNING:Xst:1780 - Signal <priority_IDs> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <arb2bus_wrack> is never used or assigned.
WARNING:Xst:1780 - Signal <grant> is never used or assigned.
Unit <opb_arbiter_core> synthesized.