plb_bram_if_cntlr_1_bram_wrapper_xst.srp

基于FPGA的防火墙系统设计.rar

Unit <plb_bram_if_cntlr_1_bram_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <plb_bram_if_cntlr_1_bram_wrapper> ...

Optimizing unit <plb_bram_if_cntlr_1_bram_elaborate> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 342

Cell Usage :
# RAMS                             : 32
#      RAMB16_S2_S2                : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                       0  out of  13696     0%  
 Number of IOs:                        342
 Number of bonded IOBs:                  0  out of    556     0%  
 Number of BRAMs:                       32  out of    136    23%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                        | Load  |
-----------------------------------+----------------------------------------------+-------+
BRAM_Clk_A                         | NONE(plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0)| 32    |
BRAM_Clk_B                         | NONE(plb_bram_if_cntlr_1_bram/ramb16_s2_s2_1)| 32    |
-----------------------------------+----------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: No path found
   Minimum input arrival time before clock: 0.219ns
   Maximum output required time after clock: 1.401ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_A'
  Total number of paths / destination ports: 512 / 512
-------------------------------------------------------------------------
Offset:              0.219ns (Levels of Logic = 1)
  Source:            BRAM_Addr_A<16> (PAD)
  Destination:       plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0 (RAM)
  Destination Clock: BRAM_Clk_A rising

  Data Path: BRAM_Addr_A<16> to plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     begin scope: 'plb_bram_if_cntlr_1_bram'
     RAMB16_S2_S2:ADDRA12        0.219          ramb16_s2_s2_0
    ----------------------------------------
    Total                      0.219ns (0.219ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_B'
  Total number of paths / destination ports: 512 / 512
-------------------------------------------------------------------------
Offset:              0.219ns (Levels of Logic = 1)
  Source:            BRAM_Addr_B<16> (PAD)
  Destination:       plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0 (RAM)
  Destination Clock: BRAM_Clk_B rising

  Data Path: BRAM_Addr_B<16> to plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     begin scope: 'plb_bram_if_cntlr_1_bram'
     RAMB16_S2_S2:ADDRB12        0.219          ramb16_s2_s2_0
    ----------------------------------------
    Total                      0.219ns (0.219ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_B'
  Total number of paths / destination ports: 64 / 64
-------------------------------------------------------------------------
Offset:              1.401ns (Levels of Logic = 1)
  Source:            plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0 (RAM)
  Destination:       BRAM_Din_B<0> (PAD)
  Source Clock:      BRAM_Clk_B rising

  Data Path: plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0 to BRAM_Din_B<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S2_S2:CLKB->DOB1    0   1.401   0.000  ramb16_s2_s2_0 (BRAM_Din_B<0>)
     end scope: 'plb_bram_if_cntlr_1_bram'
    ----------------------------------------
    Total                      1.401ns (1.401ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_A'
  Total number of paths / destination ports: 64 / 64
-------------------------------------------------------------------------
Offset:              1.401ns (Levels of Logic = 1)
  Source:            plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0 (RAM)
  Destination:       BRAM_Din_A<0> (PAD)
  Source Clock:      BRAM_Clk_A rising

  Data Path: plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0 to BRAM_Din_A<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S2_S2:CLKA->DOA1    0   1.401   0.000  ramb16_s2_s2_0 (BRAM_Din_A<0>)
     end scope: 'plb_bram_if_cntlr_1_bram'
    ----------------------------------------
    Total                      1.401ns (1.401ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 35.17 / 35.47 s | Elapsed : 35.00 / 36.00 s
 
--> 

Total memory usage is 187968 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   36 (   0 filtered)
Number of infos    :    1 (   0 filtered)